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Results: 1-7 |
Results: 7
Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout
Authors: Baldick, R Kahng, AB Kennings, A Markov, IL
Citation: R. Baldick et al., Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout, IEEE CIRC-I, 48(8), 2001, pp. 947-956
Constraint-based watermarking techniques for design IP protection
Authors: Kahng, AB Lach, J Mangione-Smith, WH Mantik, S Markov, IL Potkonjak, M Tucker, P Wang, HJ Wolfe, G
Citation: Ab. Kahng et al., Constraint-based watermarking techniques for design IP protection, IEEE COMP A, 20(10), 2001, pp. 1236-1252
Iterative partitioning with varying node weights
Authors: Caldwell, AE Kahng, AB Markov, IL
Citation: Ae. Caldwell et al., Iterative partitioning with varying node weights, VLSI DESIGN, 11(3), 2000, pp. 249-258
Hypergraph partitioning with fixed vertices
Authors: Alpert, CJ Caldwell, AE Kahng, AB Markov, IL
Citation: Cj. Alpert et al., Hypergraph partitioning with fixed vertices, IEEE COMP A, 19(2), 2000, pp. 267-272
Optimal partitioners and end-case placers for standard-cell layout
Authors: Caldwell, AE Kahng, AB Markov, IL
Citation: Ae. Caldwell et al., Optimal partitioners and end-case placers for standard-cell layout, IEEE COMP A, 19(11), 2000, pp. 1304-1313
Analytical engines are unnecessary in top-down partitioning-based placement
Authors: Alpert, CJ Caldwell, AE Chan, TF Huang, DJH Kahng, AB Markov, IL Moroz, MS
Citation: Cj. Alpert et al., Analytical engines are unnecessary in top-down partitioning-based placement, VLSI DESIGN, 10(1), 1999, pp. 99-116
On wirelength estimations for row-based placement
Authors: Caldwell, AE Kahng, AB Mantik, S Markov, IL Zelikovsky, A
Citation: Ae. Caldwell et al., On wirelength estimations for row-based placement, IEEE COMP A, 18(9), 1999, pp. 1265-1278
Risultati: 1-7 |