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Results:
1-8
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Results: 8
Authors:
Zhong, P
Martonosi, M
Ashar, P
Citation: P. Zhong et al., FPGA-based SAT solver architecture with near-zero synthesis and layout overhead, IEE P-COM D, 147(3), 2000, pp. 135-141
Authors:
Luo, Z
Martonosi, M
Ashar, P
Citation: Z. Luo et al., An edge-endpoint-based configurable hardware architecture for VLSI layout Design Rule Checking, VLSI DESIGN, 10(3), 2000, pp. 249-263
Authors:
Brooks, D
Martonosi, M
Citation: D. Brooks et M. Martonosi, Value-based clock gating and operation packing: Dynamic strategies for improving processor power and performance, ACM T COMP, 18(2), 2000, pp. 89-126
Authors:
Stenstrom, P
Hagersten, E
Lilja, DJ
Martonosi, M
Venugopal, M
Citation: P. Stenstrom et al., Shared-memory multiprocessing: Current state and future directions, ADV COMPUT, 53, 2000, pp. 1-53
Authors:
Luo, Z
Martonosi, M
Citation: Z. Luo et M. Martonosi, Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques, IEEE COMPUT, 49(3), 2000, pp. 208-218
Authors:
Zhong, PX
Martonosi, M
Ashar, P
Malik, S
Citation: Px. Zhong et al., Using configurable computing to accelerate Boolean satisfiability, IEEE COMP A, 18(6), 1999, pp. 861-868
Authors:
Ghosh, S
Martonosi, M
Malik, S
Citation: S. Ghosh et al., Cache Miss Equations: A compiler framework for analyzing and tuning memorybehavior, ACM T PROGR, 21(4), 1999, pp. 703-746
Authors:
Skadron, K
Ahuja, PS
Martonosi, M
Clark, DW
Citation: K. Skadron et al., Branch prediction, instruction-window size, and cache size: Performance trade-offs and simulation techniques, IEEE COMPUT, 48(11), 1999, pp. 1260-1281
Risultati:
1-8
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