Authors:
OHHATA K
KUSUNOKI T
NAMBU H
KANETANI K
MASUDA T
OHAYASHI M
HAMAMOTO S
YAMAGUCHI K
IDEI Y
HOMMA N
Citation: K. Ohhata et al., REDUNDANCY CIRCUIT FOR A SUBNANOSECOND, MEGABIT ECL-CMOS SRAM, IEICE transactions on electronics, E79C(3), 1996, pp. 415-423
Authors:
OHHATA K
NAMBU H
KANETANI K
MASUDA T
KUSUNOKI T
HOMMA N
Citation: K. Ohhata et al., A BICMOS CIRCUIT USING A BASE-BOOST TECHNIQUE FOR LOW-VOLTAGE, LOW-POWER APPLICATION, IEICE transactions on electronics, E79C(12), 1996, pp. 1658-1665
Authors:
HIGETA K
USAMI M
OHAYASHI M
FUJIMURA Y
NISHIYAMA M
ISOMURA S
YAMAGUCHI K
IDEI Y
NAMBU H
OHHATA K
HANTA N
Citation: K. Higeta et al., A SOFT-ERROR-IMMUNE 0.9-NS 1.15-MB ECL-CMOS SRAM WITH 30-PS 120 K LOGIC GATES AND ON-CHIP TEST CIRCUITRY, IEEE journal of solid-state circuits, 31(10), 1996, pp. 1443-1450
Authors:
OHHATA K
SAKURAI Y
NAMBU H
KANETANI K
IDEI Y
HIRAMOTO T
TAMBA N
YAMAGUCHI K
ODAKA M
WATANABE K
IKEDA T
HOMMA N
Citation: K. Ohhata et al., NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME, IEICE transactions on electronics, E76C(11), 1993, pp. 1611-1619