AAAAAA

   
Results: 1-8 |
Results: 8
DESIGN OF A 2-NS CYCLE TIME 72-KB ECL-CMOS SRAM MACRO
Authors: OHHATA K KUSUNOKI T NAMBU H KANETANI K HIGETA K YAMAGUCHI K HOMMA N
Citation: K. Ohhata et al., DESIGN OF A 2-NS CYCLE TIME 72-KB ECL-CMOS SRAM MACRO, IEICE transactions on electronics, E81C(3), 1998, pp. 447-454
REDUNDANCY CIRCUIT FOR A SUBNANOSECOND, MEGABIT ECL-CMOS SRAM
Authors: OHHATA K KUSUNOKI T NAMBU H KANETANI K MASUDA T OHAYASHI M HAMAMOTO S YAMAGUCHI K IDEI Y HOMMA N
Citation: K. Ohhata et al., REDUNDANCY CIRCUIT FOR A SUBNANOSECOND, MEGABIT ECL-CMOS SRAM, IEICE transactions on electronics, E79C(3), 1996, pp. 415-423
A BICMOS CIRCUIT USING A BASE-BOOST TECHNIQUE FOR LOW-VOLTAGE, LOW-POWER APPLICATION
Authors: OHHATA K NAMBU H KANETANI K MASUDA T KUSUNOKI T HOMMA N
Citation: K. Ohhata et al., A BICMOS CIRCUIT USING A BASE-BOOST TECHNIQUE FOR LOW-VOLTAGE, LOW-POWER APPLICATION, IEICE transactions on electronics, E79C(12), 1996, pp. 1658-1665
A SOFT-ERROR-IMMUNE 0.9-NS 1.15-MB ECL-CMOS SRAM WITH 30-PS 120 K LOGIC GATES AND ON-CHIP TEST CIRCUITRY
Authors: HIGETA K USAMI M OHAYASHI M FUJIMURA Y NISHIYAMA M ISOMURA S YAMAGUCHI K IDEI Y NAMBU H OHHATA K HANTA N
Citation: K. Higeta et al., A SOFT-ERROR-IMMUNE 0.9-NS 1.15-MB ECL-CMOS SRAM WITH 30-PS 120 K LOGIC GATES AND ON-CHIP TEST CIRCUITRY, IEEE journal of solid-state circuits, 31(10), 1996, pp. 1443-1450
A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM
Authors: NAMBU H KANETANI K IDEI Y MASUDA T HIGETA K OHAYASHI M USAMI M YAMAGUCHI K KIKUCHI T IKEDA T OHHATA K KUSUNOKI T HOMMA N
Citation: H. Nambu et al., A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM, IEICE transactions on electronics, E78C(6), 1995, pp. 739-747
A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM
Authors: NAMBU H KANETANI K IDEI Y MASUDA T HIGETA K OHAYASHI M USAMI M YAMAGUCHI K KIKUCHI T IKEDA T OHHATA K KUSUNOKI T HOMMA N
Citation: H. Nambu et al., A 0.65-NS, 72-KB ECL-CMOS RAM MACRO FOR A 1-MB SRAM, IEEE journal of solid-state circuits, 30(4), 1995, pp. 491-499
REDUNDANCY TECHNIQUE FOR ULTRA-HIGH-SPEED STATIC RAMS
Authors: NAMBU H KANETANI K IDEI Y YAMAGUCHI K HIRAMOTO T TAMBA N WATANABE K ODAKA M IKEDA T OHHATA K SAKURAI Y HOMMA N
Citation: H. Nambu et al., REDUNDANCY TECHNIQUE FOR ULTRA-HIGH-SPEED STATIC RAMS, IEICE transactions on electronics, E76C(4), 1993, pp. 641-648
NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME
Authors: OHHATA K SAKURAI Y NAMBU H KANETANI K IDEI Y HIRAMOTO T TAMBA N YAMAGUCHI K ODAKA M WATANABE K IKEDA T HOMMA N
Citation: K. Ohhata et al., NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME, IEICE transactions on electronics, E76C(11), 1993, pp. 1611-1619
Risultati: 1-8 |