Authors:
NAKAMURA H
MIYAMOTO J
IMAMIYA K
IWATA Y
SUGIURA Y
OODAIRA H
Citation: H. Nakamura et al., A NOVEL SENSING SCHEME WITH ON-CHIP PAGE COPY FOR FLEXIBLE VOLTAGE NAND FLASH MEMORIES, IEICE transactions on electronics, E79C(6), 1996, pp. 836-844
Authors:
TANAKA T
TANAKA Y
NAKAMURA H
SAKUI K
OODAIRA H
SHIROTA R
OHUCHI K
MASUOKA F
HARA H
Citation: T. Tanaka et al., A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1366-1373
Authors:
TANAKA T
TANAKA Y
NAKAMURA H
SAKUI K
OODAIRA H
SHIROTA R
OHUCHI K
MASUOKA F
HARA H
Citation: T. Tanaka et al., A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1366-1373