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Results: 1-11 |
Results: 11
SIMULATION OF LOSSY MULTICONDUCTOR TRANSMISSION-LINES USING BACKWARD EULER INTEGRATION
Authors: CELIK M PILEGGI LT
Citation: M. Celik et Lt. Pileggi, SIMULATION OF LOSSY MULTICONDUCTOR TRANSMISSION-LINES USING BACKWARD EULER INTEGRATION, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 45(3), 1998, pp. 238-243
PRIMA - PASSIVE REDUCED-ORDER INTERCONNECT MACROMODELING ALGORITHM
Authors: ODABASIOGLU A CELIK M PILEGGI LT
Citation: A. Odabasioglu et al., PRIMA - PASSIVE REDUCED-ORDER INTERCONNECT MACROMODELING ALGORITHM, IEEE transactions on computer-aided design of integrated circuits and systems, 17(8), 1998, pp. 645-654
EWA - EFFICIENT WIRING-SIZING ALGORITHM FOR SIGNAL NETS AND CLOCK NETS
Authors: KAY R PILEGGI LT
Citation: R. Kay et Lt. Pileggi, EWA - EFFICIENT WIRING-SIZING ALGORITHM FOR SIGNAL NETS AND CLOCK NETS, IEEE transactions on computer-aided design of integrated circuits and systems, 17(1), 1998, pp. 40-49
A SEQUENTIAL QUADRATIC-PROGRAMMING APPROACH TO CONCURRENT GATE AND WIRE SIZING
Authors: MENEZES N BALDICK R PILEGGI LT
Citation: N. Menezes et al., A SEQUENTIAL QUADRATIC-PROGRAMMING APPROACH TO CONCURRENT GATE AND WIRE SIZING, IEEE transactions on computer-aided design of integrated circuits and systems, 16(8), 1997, pp. 867-881
MOMENT-SENSITIVITY-BASED WIRE SIZING FOR SKEW REDUCTION IN ON-CHIP CLOCK NETS
Authors: PULLELA S MENEZES N PILEGGI LT
Citation: S. Pullela et al., MOMENT-SENSITIVITY-BASED WIRE SIZING FOR SKEW REDUCTION IN ON-CHIP CLOCK NETS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(2), 1997, pp. 210-215
TRANSMISSION-LINE SYNTHESIS VIA CONSTRAINED MULTIVARIABLE OPTIMIZATION
Authors: GUPTA R KRAUTER B PILEGGI LT
Citation: R. Gupta et al., TRANSMISSION-LINE SYNTHESIS VIA CONSTRAINED MULTIVARIABLE OPTIMIZATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(1), 1997, pp. 6-19
THE ELMORE DELAY AS A BOUND FOR RC TREES WITH GENERALIZED INPUT SIGNALS
Authors: GUPTA R TUTUIANU B PILEGGI LT
Citation: R. Gupta et al., THE ELMORE DELAY AS A BOUND FOR RC TREES WITH GENERALIZED INPUT SIGNALS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(1), 1997, pp. 95-104
MODELING LOSSY TRANSMISSION-LINES USING THE METHOD OF CHARACTERISTICS
Authors: GUPTA R PILEGGI LT
Citation: R. Gupta et Lt. Pileggi, MODELING LOSSY TRANSMISSION-LINES USING THE METHOD OF CHARACTERISTICS, IEEE transactions on circuits and systems. 1, Fundamental theory andapplications, 43(7), 1996, pp. 580-582
POST-PROCESSING OF CLOCK TREES VIA WIRESIZING AND BUFFERING FOR ROBUST DESIGN
Authors: PULLELA S MENEZES N PILEGGI LT
Citation: S. Pullela et al., POST-PROCESSING OF CLOCK TREES VIA WIRESIZING AND BUFFERING FOR ROBUST DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 15(6), 1996, pp. 691-701
PERFORMANCE COMPUTATION FOR PRECHARACTERIZED CMOS GATES WITH RC LOADS
Authors: DARTU F MENEZES N PILEGGI LT
Citation: F. Dartu et al., PERFORMANCE COMPUTATION FOR PRECHARACTERIZED CMOS GATES WITH RC LOADS, IEEE transactions on computer-aided design of integrated circuits and systems, 15(5), 1996, pp. 544-553
DOMAIN CHARACTERIZATION OF TRANSMISSION-LINE MODELS AND ANALYSES
Authors: GUPTA R KIM SY PILEGGI LT
Citation: R. Gupta et al., DOMAIN CHARACTERIZATION OF TRANSMISSION-LINE MODELS AND ANALYSES, IEEE transactions on computer-aided design of integrated circuits and systems, 15(2), 1996, pp. 184-193
Risultati: 1-11 |