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Results: 1-25 | 26-35 |
Results: 26-35/35
TAG AND CONTOUR-DETECTION IN TAGGED MR-IMAGES OF THE LEFT-VENTRICLE
Authors: GUTTMAN MA PRINCE JL MCVEIGH ER
Citation: Ma. Guttman et al., TAG AND CONTOUR-DETECTION IN TAGGED MR-IMAGES OF THE LEFT-VENTRICLE, IEEE transactions on medical imaging, 13(1), 1994, pp. 74-88
REFERENCE PLANE PARASITICS MODELING AND THEIR CONTRIBUTION TO THE POWER AND GROUND PATH EFFECTIVE INDUCTANCE AS SEEN BY THE OUTPUT DRIVERS
Authors: SENTHINATHAN R CANGELLARIS AC PRINCE JL
Citation: R. Senthinathan et al., REFERENCE PLANE PARASITICS MODELING AND THEIR CONTRIBUTION TO THE POWER AND GROUND PATH EFFECTIVE INDUCTANCE AS SEEN BY THE OUTPUT DRIVERS, IEEE transactions on microwave theory and techniques, 42(9), 1994, pp. 1765-1773
RIGOROUS ELECTROMAGNETIC MODELING OF CHIP-TO-PACKAGE (1ST-LEVEL) INTERCONNECTIONS
Authors: TSUEI YS CANGELLARIS AC PRINCE JL
Citation: Ys. Tsuei et al., RIGOROUS ELECTROMAGNETIC MODELING OF CHIP-TO-PACKAGE (1ST-LEVEL) INTERCONNECTIONS, IEEE transactions on components, hybrids, and manufacturing technology, 16(8), 1993, pp. 876-883
MODELING AND SIMULATION OF COUPLED TRANSMISSION-LINE INTERCONNECTS OVER A NOISY REFERENCE PLANE
Authors: SENTHINATHAN R NIMMAGADDA S PRINCE JL CANGELLARIS AC
Citation: R. Senthinathan et al., MODELING AND SIMULATION OF COUPLED TRANSMISSION-LINE INTERCONNECTS OVER A NOISY REFERENCE PLANE, IEEE transactions on components, hybrids, and manufacturing technology, 16(7), 1993, pp. 705-713
MODULE FREQUENCY ESTIMATION AND NOISE BUDGET LIMITATIONS - TRADE-OFFSIN MULTICHIP MODULES AS A FUNCTION OF CMOS CHIPS INTEGRATION
Authors: SENTHINATHAN R PRINCE JL CANGELLARIS AC
Citation: R. Senthinathan et al., MODULE FREQUENCY ESTIMATION AND NOISE BUDGET LIMITATIONS - TRADE-OFFSIN MULTICHIP MODULES AS A FUNCTION OF CMOS CHIPS INTEGRATION, IEEE transactions on components, hybrids, and manufacturing technology, 16(5), 1993, pp. 478-483
FINITE-DIFFERENCE TIME-DOMAIN ANALYSIS OF PULSE-PROPAGATION IN MULTICHIP-MODULE INTERCONNECTS
Authors: GRIBBONS M CANGELLARIS AC PRINCE JL
Citation: M. Gribbons et al., FINITE-DIFFERENCE TIME-DOMAIN ANALYSIS OF PULSE-PROPAGATION IN MULTICHIP-MODULE INTERCONNECTS, IEEE transactions on components, hybrids, and manufacturing technology, 16(5), 1993, pp. 490-498
ELECTRICAL CHARACTERISTICS OF MULTICHIP MODULE INTERCONNECTS WITH PERFORATED REFERENCE PLANES
Authors: CANGELLARIS AC GRIBBONS M PRINCE JL
Citation: Ac. Cangellaris et al., ELECTRICAL CHARACTERISTICS OF MULTICHIP MODULE INTERCONNECTS WITH PERFORATED REFERENCE PLANES, IEEE transactions on components, hybrids, and manufacturing technology, 16(1), 1993, pp. 113-118
CROSSTALK ANALYSIS FOR HIGH-SPEED PULSE-PROPAGATION IN LOSSY ELECTRICAL INTERCONNECTIONS
Authors: VORANANTAKUL S PRINCE JL HSU P
Citation: S. Voranantakul et al., CROSSTALK ANALYSIS FOR HIGH-SPEED PULSE-PROPAGATION IN LOSSY ELECTRICAL INTERCONNECTIONS, IEEE transactions on components, hybrids, and manufacturing technology, 16(1), 1993, pp. 127-136
EFFICIENT COMPUTATION OF SIGNAL PROPAGATION DELAY WITH OVERSHOOT-CONTROL AND UNDERSHOOT-CONTROL IN VLSI INTERCONNECTIONS
Authors: VORANANTAKUL S PRINCE JL
Citation: S. Voranantakul et Jl. Prince, EFFICIENT COMPUTATION OF SIGNAL PROPAGATION DELAY WITH OVERSHOOT-CONTROL AND UNDERSHOOT-CONTROL IN VLSI INTERCONNECTIONS, IEEE transactions on components, hybrids, and manufacturing technology, 16(1), 1993, pp. 146-151
APPLICATION-SPECIFIC CMOS OUTPUT DRIVER CIRCUIT-DESIGN TECHNIQUES TO REDUCE SIMULTANEOUS SWITCHING NOISE
Authors: SENTHINATHAN R PRINCE JL
Citation: R. Senthinathan et Jl. Prince, APPLICATION-SPECIFIC CMOS OUTPUT DRIVER CIRCUIT-DESIGN TECHNIQUES TO REDUCE SIMULTANEOUS SWITCHING NOISE, IEEE journal of solid-state circuits, 28(12), 1993, pp. 1383-1388
Risultati: 1-25 | 26-35 |