Authors: Pavanello, MA Martino, JA Dessard, V Flandre, D

Citation: Ma. Pavanello et al., An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics, EL SOLID ST, 3(1), 2000, pp. 50-52

Authors: Pavanello, MA Martino, JA Dessard, V Flandre, D

Citation: Ma. Pavanello et al., Analog performance and application of graded-channel fully depleted SOI MOSFETs, SOL ST ELEC, 44(7), 2000, pp. 1219-1222

Authors: Pavanello, MA Martino, JA Flandre, D

Citation: Ma. Pavanello et al., Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects, SOL ST ELEC, 44(6), 2000, pp. 917-922

Authors: Pavanello, MA Martino, JA

Citation: Ma. Pavanello et Ja. Martino, Extraction of the oxide charges at the silicon substrate interface in Silicon-On-Insulator MOSFET's, SOL ST ELEC, 43(11), 1999, pp. 2039-2046