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Results: 1-10 |
Results: 10
Discrete-time battery models for system-level low-power design
Authors: Benini, L Castelli, G Macii, A Mach, E Poncino, M Scarsi, R
Citation: L. Benini et al., Discrete-time battery models for system-level low-power design, IEEE VLSI, 9(5), 2001, pp. 630-640
Stream synthesis for efficient power simulation based on spectral transforms
Authors: Macii, A Macii, E Poncino, M Scarsi, R
Citation: A. Macii et al., Stream synthesis for efficient power simulation based on spectral transforms, IEEE VLSI, 9(3), 2001, pp. 417-426
Synthesis of power-managed sequential components based on computational kernel extraction
Authors: Benini, L De Micheli, G Lioy, A Macii, E Odasso, G Poncino, M
Citation: L. Benini et al., Synthesis of power-managed sequential components based on computational kernel extraction, IEEE COMP A, 20(9), 2001, pp. 1118-1131
Glitch power minimization by selective gate freezing
Authors: Benini, L De Micheli, D Macii, A Macii, E Poncino, M Scarsi, R
Citation: L. Benini et al., Glitch power minimization by selective gate freezing, IEEE VLSI, 8(3), 2000, pp. 287-298
Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation
Authors: Benini, L Macii, A Macii, E Poncino, M
Citation: L. Benini et al., Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation, IEEE DES T, 17(2), 2000, pp. 74-85
Architectures and synthesis algorithms for power-efficient bus interfaces
Authors: Benini, L Macii, A Macii, E Poncino, M Scarsi, R
Citation: L. Benini et al., Architectures and synthesis algorithms for power-efficient bus interfaces, IEEE COMP A, 19(9), 2000, pp. 969-980
Symbolic optimization of interacting controllers based on redundancy identification and removal
Authors: Ferrandi, F Fummi, F Macii, E Poncino, M Sciuto, D
Citation: F. Ferrandi et al., Symbolic optimization of interacting controllers based on redundancy identification and removal, IEEE COMP A, 19(7), 2000, pp. 760-772
A multilevel engine for fast power simulation of realistic input streams
Authors: Benini, L De Micheli, G Macii, E Poncino, M Scarsi, R
Citation: L. Benini et al., A multilevel engine for fast power simulation of realistic input streams, IEEE COMP A, 19(4), 2000, pp. 459-472
Automatic selection of instruction op-codes of low-power core processors
Authors: Benini, L De Micheli, G Macii, A Macii, E Poncino, M
Citation: L. Benini et al., Automatic selection of instruction op-codes of low-power core processors, IEE P-COM D, 146(4), 1999, pp. 173-178
Automatic synthesis of large telescopic units based on near-minimum timed supersetting
Authors: Benini, L De Micheli, G Lioy, A Macii, E Odasso, G Poncino, M
Citation: L. Benini et al., Automatic synthesis of large telescopic units based on near-minimum timed supersetting, IEEE COMPUT, 48(8), 1999, pp. 769-779
Risultati: 1-10 |