Login
|
New Account
AAAAAA
ITA
ENG
Results:
1-3
|
Results: 3
Delay fault testing: Choosing between random SIC and random MIC test sequences
Authors:
Virazel, A David, R Girard, P Landrault, C Pravossoudovitch, S
Citation:
A. Virazel et al., Delay fault testing: Choosing between random SIC and random MIC test sequences, J ELEC TEST, 17(3-4), 2001, pp. 233-241
Low power BIST by filtering non-detecting vectors
Authors:
Manich, S Gabarro, A Lopez, M Figueras, J Girard, P Guiller, L Landrault, C Pravossoudovitch, S Teixeira, P Santos, M
Citation:
S. Manich et al., Low power BIST by filtering non-detecting vectors, J ELEC TEST, 16(3), 2000, pp. 193-202
A scan-BIST structure to test delay faults in sequential circuits
Authors:
Girard, P Landrault, C Moreda, V Pravossoudovitch, S Virazel, A
Citation:
P. Girard et al., A scan-BIST structure to test delay faults in sequential circuits, J ELEC TEST, 14(1-2), 1999, pp. 95-102
Risultati:
1-3
|