Authors: Puchner, H Liu, YC Kong, W Duan, F Castagnetti, R

Citation: H. Puchner et al., Substrate engineering to improve soft-error-rate immunity for SRAM technologies, MICROEL REL, 41(9-10), 2001, pp. 1319-1324

Authors: Palankovski, V Belova, N Grasser, T Puchner, H Aronowitz, S Selberherr, S

Citation: V. Palankovski et al., A methodology for deep sub-0.25 mu m CMOS technology prediction, IEEE DEVICE, 48(10), 2001, pp. 2331-2336

Authors: Puchner, H Castagnetti, R Pyka, W

Citation: H. Puchner et al., Minimizing thick resist sidewall slope dependence on design geometry by optimizing bake conditions, MICROEL ENG, 53(1-4), 2000, pp. 429-432

Authors: Sukharev, V Aronowitz, S Zubkov, V Puchner, H Haywood, J Kimball, J

Citation: V. Sukharev et al., Plasma-induced nitridation of gate oxide dielectrics: Linked equipment-feature atomic scale simulations, J VAC SCI A, 17(4), 1999, pp. 1356-1363

Authors: Aronowitz, S Puchner, H Kimball, J

Citation: S. Aronowitz et al., Optimized subamorphizing silicon implants to modify diffusion and activation of arsenic, boron, and phosphorus implants for shallow junction creation, J APPL PHYS, 85(7), 1999, pp. 3494-3498