AAAAAA
Results:
1-8
|
Results: 8
Authors:
Fummi, F
Boschini, M
Yu, XM
Rudnick, EM
Citation: F. Fummi et al., Sequential circuit test generation using a symbolic/genetic hybrid approach, J ELEC TEST, 17(3-4), 2001, pp. 321-330
Authors:
Niggemeyer, D
Stephano, KJ
Rudnick, EM
Citation: D. Niggemeyer et al., Use of a field programmable gate array for education in manufacturing testand automatic test equipment, IEEE EDUCAT, 44(3), 2001, pp. 239-245
Authors:
Hsiao, MS
Rudnick, EM
Patel, JH
Citation: Ms. Hsiao et al., Dynamic state traversal for sequential circuit test generation, ACM T DES A, 5(3), 2000, pp. 548-565
Authors:
Hsiao, MS
Rudnick, EM
Patel, JH
Citation: Ms. Hsiao et al., Peak power estimation of VLSI circuits: New peak power measures, IEEE VLSI, 8(4), 2000, pp. 435-439
Authors:
Chang, TC
Iyengar, V
Rudnick, EM
Citation: Tc. Chang et al., A biased random instruction generation environment for architectural verification of pipelined processors, J ELEC TEST, 16(1-2), 2000, pp. 13-27
Authors:
Wu, J
Rudnick, EM
Citation: J. Wu et Em. Rudnick, Bridge fault diagnosis using stuck-at fault simulation, IEEE COMP A, 19(4), 2000, pp. 489-495
Authors:
Hsiao, MS
Rudnick, EM
Patel, JH
Citation: Ms. Hsiao et al., Fast static compaction algorithms for sequential circuit test vectors, IEEE COMPUT, 48(3), 1999, pp. 311-322
Authors:
Rudnick, EM
Patel, JH
Citation: Em. Rudnick et Jh. Patel, Efficient techniques for dynamic test sequence compaction, IEEE COMPUT, 48(3), 1999, pp. 323-330
Risultati:
1-8
|