Authors: Kay, R Rutenbar, RA

Citation: R. Kay et Ra. Rutenbar, Wire packing - A strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution, IEEE COMP A, 20(5), 2001, pp. 672-679

Authors: Tong, JYF Nagle, D Rutenbar, RA

Citation: Jyf. Tong et al., Reducing power by optimizing the necessary precision/range of floating-point arithmetic, IEEE VLSI, 8(3), 2000, pp. 273-286

Authors: Mukherjee, T Carley, R Rutenbar, RA

Citation: T. Mukherjee et al., Efficient handling of operating range and manufacturing line variations inanalog cell synthesis, IEEE COMP A, 19(8), 2000, pp. 825-839

Authors: Phelps, R Krasnicki, M Rutenbar, RA Carley, LR Hellums, JR

Citation: R. Phelps et al., Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search, IEEE COMP A, 19(6), 2000, pp. 703-717

Authors: Gielen, GGE Rutenbar, RA

Citation: Gge. Gielen et Ra. Rutenbar, Computer-aided design of analog and mixed-signal integrated circuits, P IEEE, 88(12), 2000, pp. 1825-1852

Authors: Aktuna, M Rutenbar, RA Carley, LR

Citation: M. Aktuna et al., Device-level early floorplanning algorithms for RF circuits, IEEE COMP A, 18(4), 1999, pp. 375-388