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Results: 3
A NONITERATIVE GATE RESIZING ALGORITHM FOR HIGH REDUCTION IN POWER-CONSUMPTION
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., A NONITERATIVE GATE RESIZING ALGORITHM FOR HIGH REDUCTION IN POWER-CONSUMPTION, Integration, 24(1), 1997, pp. 37-52
TECHNIQUE FOR REDUCING POWER-CONSUMPTION IN CMOS CIRCUITS
Authors: GIRARD P LANDRAULT C PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., TECHNIQUE FOR REDUCING POWER-CONSUMPTION IN CMOS CIRCUITS, Electronics Letters, 33(6), 1997, pp. 485-486
REDUCTION OF POWER-CONSUMPTION DURING TEST APPLICATION BY TEST VECTORORDERING
Authors: GIRARD P LANDRAULT G PRAVOSSOUDOVITCH S SEVERAC D
Citation: P. Girard et al., REDUCTION OF POWER-CONSUMPTION DURING TEST APPLICATION BY TEST VECTORORDERING, Electronics Letters, 33(21), 1997, pp. 1752-1754
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