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Results:
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Results: 15
Authors:
MASSELOS K
MERAKOS P
STOURAITIS T
GOUTIS CE
Citation: K. Masselos et al., TRADE-OFF ANALYSIS OF A LOW-POWER IMAGE-CODING ALGORITHM, Journal of VLSI signal processing systems for signal, image, and video technology, 18(1), 1998, pp. 65-80
Authors:
KARAGIANNI K
CHRONOPOULOS T
TZES A
KOUSSOULAS N
STOURAITIS T
Citation: K. Karagianni et al., EFFICIENT PROCESSOR ARRAYS FOR THE IMPLEMENTATION OF THE GENERALIZED PREDICTIVE-CONTROL ALGORITHM, IEE proceedings. Control theory and applications, 145(1), 1998, pp. 47-54
Authors:
MASSELOS K
MERAKOS P
STOURAITIS T
GOUTIS CE
Citation: K. Masselos et al., A NOVEL ALGORITHM FOR LOW-POWER IMAGE AND VIDEO CODING, IEEE transactions on circuits and systems for video technology, 8(3), 1998, pp. 258-263
Authors:
STOURAITIS T
Citation: T. Stouraitis, ICECS POST-CONFERENCE REPORT, IEEE circuits and devices magazine, 13(2), 1997, pp. 48-48
Authors:
SOUDRIS DJ
PALIOURAS V
STOURAITIS T
THANAILAKIS A
Citation: Dj. Soudris et al., DESIGN METHODOLOGY FOR THE IMPLEMENTATION OF MULTIDIMENSIONAL CIRCULAR CONVOLUTION, IEE proceedings. Circuits, devices and systems, 144(6), 1997, pp. 323-328
Authors:
SOUDRIS DJ
PALIOURAS V
STOURAITIS T
GOUTIS CE
Citation: Dj. Soudris et al., A VLSI DESIGN METHODOLOGY FOR RNS FULL ADDER-BASED INNER-PRODUCT ARCHITECTURES, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(4), 1997, pp. 315-318
Authors:
TATSAKI A
DRE C
STOURAITIS T
GOUTIS C
Citation: A. Tatsaki et al., PRIME-FACTOR DCT ALGORITHMS, IEEE transactions on signal processing, 43(3), 1995, pp. 772-776
Authors:
TATSAKI A
DRE C
STOURAITIS T
GOUTIS C
Citation: A. Tatsaki et al., ON THE COMPUTATION OF THE PRIME FACTOR DST, Signal processing, 42(3), 1995, pp. 231-236
Authors:
TATSAKI A
STOURAITIS T
GOUTIS C
Citation: A. Tatsaki et al., IMAGE CODER BASED ON RESIDUE NUMBER SYSTEM FOR PROGRESSIVE TRANSMISSION, Electronics Letters, 31(6), 1995, pp. 442-443
Authors:
STOURAITIS T
Citation: T. Stouraitis, ANALOG-TO-RESIDUE AND BINARY-TO-RESIDUE CONVERSION SCHEMES, IEE proceedings. Circuits, devices and systems, 141(2), 1994, pp. 135-139
Authors:
STOURAITIS T
Citation: T. Stouraitis, PERFORMANCE EVALUATION OF BIN ABIN NETWORKS IN BUFFERED UNBUFFERED PACKET-SWITCHED ENVIRONMENTS, IEE proceedings. Computers and digital techniques, 141(1), 1994, pp. 29-34
Authors:
SKAVANTZOS A
STOURAITIS T
Citation: A. Skavantzos et T. Stouraitis, POLYNOMIAL RESIDUE COMPLEX SIGNAL-PROCESSING, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 40(5), 1993, pp. 342-344
Authors:
STOURAITIS T
KIM SW
SKAVANTZOS A
Citation: T. Stouraitis et al., FULL ADDER-BASED ARITHMETIC UNITS FOR FINITE INTEGER RINGS, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 40(11), 1993, pp. 740-745
Authors:
STOURAITIS T
CHEN C
Citation: T. Stouraitis et C. Chen, HYBRID SIGNED-DIGIT LOGARITHMIC NUMBER SYSTEM PROCESSOR, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 205-210
Authors:
STOURAITIS T
Citation: T. Stouraitis, BORROW - A FAULT-TOLERANCE SCHEME FOR WAVE-FRONT ARRAY PROCESSORS, I.E.E.E. transactions on computers, 42(10), 1993, pp. 1257-1261
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1-15
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