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Citation: Hp. Tseng et al., Timing- and crosstalk-driven area routing, IEEE COMP A, 20(4), 2001, pp. 528-544

Authors: Yee, G Sechen, C

Citation: G. Yee et C. Sechen, Clock-delayed domino for dynamic circuit design, IEEE VLSI, 8(4), 2000, pp. 425-430

Authors: Liu, LCE Sechen, C

Citation: Lce. Liu et C. Sechen, Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic, IEEE COMP A, 18(10), 1999, pp. 1442-1451

Authors: Liu, LCE Sechen, C

Citation: Lce. Liu et C. Sechen, Multilayer pin assignment for macro cell circuits, IEEE COMP A, 18(10), 1999, pp. 1452-1461

Authors: Tseng, HP Sechen, C

Citation: Hp. Tseng et C. Sechen, A gridless multilayer router for standard cell circuits using CTM cells, IEEE COMP A, 18(10), 1999, pp. 1462-1479