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Results:
1-4
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Results: 4
3-D ICs: A novel chip design for improving deep-submicrometer interconnectperformance and systems-on-chip integration
Authors:
Banerjee, K Souri, SJ Kapur, P Saraswat, KC
Citation:
K. Banerjee et al., 3-D ICs: A novel chip design for improving deep-submicrometer interconnectperformance and systems-on-chip integration, P IEEE, 89(5), 2001, pp. 602-633
Interconnect limits on gigascale integration (GSI) in the 21st century
Authors:
Davis, JA Venkatesan, R Kaloyeros, A Beylansky, M Souri, SJ Banerjee, K Saraswat, KC Rahman, A Reif, R Meindl, JD
Citation:
Ja. Davis et al., Interconnect limits on gigascale integration (GSI) in the 21st century, P IEEE, 89(3), 2001, pp. 305-324
Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFT's for vertical integration applications
Authors:
Subramanian, V Toita, M Ibrahim, NR Souri, SJ Saraswat, KC
Citation:
V. Subramanian et al., Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFT's for vertical integration applications, IEEE ELEC D, 20(7), 1999, pp. 341-343
Varistor behavior at twin boundaries in ZnO
Authors:
Haskell, BA Souri, SJ Helfand, MA
Citation:
Ba. Haskell et al., Varistor behavior at twin boundaries in ZnO, J AM CERAM, 82(8), 1999, pp. 2106-2110
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