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Results: 1-4 |
Results: 4
ACCURATE BASE AND COLLECTOR CURRENT MODELING OF POLYSILICON EMITTER BIPOLAR-TRANSISTORS - QUANTIFICATION OF HOLE SURFACE RECOMBINATION VELOCITY
Authors: KIZILYALLI IC RAMBAUD MM HAM TE STEVIE FA KAHORA PM ZANESKI G THOMA MJ BOULIN DM
Citation: Ic. Kizilyalli et al., ACCURATE BASE AND COLLECTOR CURRENT MODELING OF POLYSILICON EMITTER BIPOLAR-TRANSISTORS - QUANTIFICATION OF HOLE SURFACE RECOMBINATION VELOCITY, Journal of applied physics, 79(5), 1996, pp. 2738-2744
HIGH-PERFORMANCE 3.3- AND 5-V 0.5-MU-M CMOS TECHNOLOGY FOR ASICS
Authors: KIZILYALLI IC THOMA MJ LYTLE SA MARTIN EP SINGH R VITKAVAGE SC BECHTOLD PF KEARNEY JW RAMBAUD MM TWIFORD MS COCHRAN WT FENSTERMAKER LR FREYMAN R SUN WS DUNCAN A
Citation: Ic. Kizilyalli et al., HIGH-PERFORMANCE 3.3- AND 5-V 0.5-MU-M CMOS TECHNOLOGY FOR ASICS, IEEE transactions on semiconductor manufacturing, 8(4), 1995, pp. 440-448
THRESHOLD VOLTAGE MINIMUM GATE LENGTH TRADE-OFF IN BURIED-CHANNEL PMOS DEVICES FOR SCALED SUPPLY VOLTAGE CMOS TECHNOLOGIES
Authors: KIZILYALLI IC RAMBAUD MM DUNCAN A LYTLE SA THOMA MJ
Citation: Ic. Kizilyalli et al., THRESHOLD VOLTAGE MINIMUM GATE LENGTH TRADE-OFF IN BURIED-CHANNEL PMOS DEVICES FOR SCALED SUPPLY VOLTAGE CMOS TECHNOLOGIES, IEEE electron device letters, 16(10), 1995, pp. 457-459
PREDICTIVE WORST CASE STATISTICAL MODELING OF 0.8-MU-M BICMOS BIPOLAR-TRANSISTORS - A METHODOLOGY BASED ON PROCESS AND MIXED DEVICE CIRCUITLEVEL SIMULATORS
Authors: KIZILYALLI IC HAM TE SINGHAL K KEARNEY JW LIN W THOMA MJ
Citation: Ic. Kizilyalli et al., PREDICTIVE WORST CASE STATISTICAL MODELING OF 0.8-MU-M BICMOS BIPOLAR-TRANSISTORS - A METHODOLOGY BASED ON PROCESS AND MIXED DEVICE CIRCUITLEVEL SIMULATORS, I.E.E.E. transactions on electron devices, 40(5), 1993, pp. 966-973
Risultati: 1-4 |