HIGH-PERFORMANCE 3.3- AND 5-V 0.5-MU-M CMOS TECHNOLOGY FOR ASICS

Process integration of two manufacturable high performance 0.5-mu m CM OS technologies, one optimized for 5.0-V operation and the second opti mized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOCOS (PBL) isolation, MOS transistor design using conv entional and statistical modeling to reduce circuit performance sensit ivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulat ion data for both 3.3- and 5.0-V technologies will be shown. The nomin al ring oscillator delay is measured for both 3.3- and 5.0-V technolog ies as 80 ps. Therefore, 5,0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a fa ctor of 2.4.