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Citation: H. Hoenigschmid et al., A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's, IEEE J SOLI, 35(5), 2000, pp. 713-718

Authors: Kirihata, T Mueller, G Ji, B Frankowsky, G Ross, JM Terletzki, H Netis, DG Weinfurtner, O Hanson, DR Daniel, G Hsu, LLC Storaska, DW Reith, AM Hug, MA Guay, KP Selz, M Poechmueller, P Hoenigschmid, H Wordeman, MR

Citation: T. Kirihata et al., A 390-mm(2), 16-bank, l-Gb DDR SDRAM with hybrid bitline architecture, IEEE J SOLI, 34(11), 1999, pp. 1580-1588