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Results: 1-10 |
Results: 10
An area/time optimizing algorithm in high-level synthesis of control-basedhardwares
Authors: Togawa, N Ienaga, M Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., An area/time optimizing algorithm in high-level synthesis of control-basedhardwares, IEICE T FUN, E84A(5), 2001, pp. 1166-1176
Area and delay estimation in hardware/software cosynthesis for digital signal processor cores
Authors: Togawa, N Kataoka, Y Miyaoka, Y Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., Area and delay estimation in hardware/software cosynthesis for digital signal processor cores, IEICE T FUN, E84A(11), 2001, pp. 2639-2647
A new hardware/software partitioning algorithm for DSP processor cores with two types of register files
Authors: Togawa, N Sakurai, T Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., A new hardware/software partitioning algorithm for DSP processor cores with two types of register files, IEICE T FUN, E84A(11), 2001, pp. 2802-2807
A hardware/software cosynthesis system for digital signal processor cores with two types of register files
Authors: Togawa, N Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., A hardware/software cosynthesis system for digital signal processor cores with two types of register files, IEICE T FUN, E83A(3), 2000, pp. 442-451
CAM processor synthesis based on behavioral descriptions
Authors: Togawa, N Wakui, T Yoden, T Terajima, M Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., CAM processor synthesis based on behavioral descriptions, IEICE T FUN, E83A(12), 2000, pp. 2464-2473
A depth-constrained technology mapping algorithm for logic-blocks composedof tree-structured LUTs
Authors: Togawa, N Ara, K Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., A depth-constrained technology mapping algorithm for logic-blocks composedof tree-structured LUTs, IEICE T FUN, E82A(3), 1999, pp. 473-482
A hardware/software cosynthesis system for digital signal processor cores
Authors: Togawa, N Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., A hardware/software cosynthesis system for digital signal processor cores, IEICE T FUN, E82A(11), 1999, pp. 2325-2337
A simultaneous placement and global routing algorithm for FPGAS with poweroptimization
Authors: Togawa, N Ukai, K Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., A simultaneous placement and global routing algorithm for FPGAS with poweroptimization, J CIR SYS C, 9(1-2), 1999, pp. 99-112
Cisplatin in combination with irinotecan in the treatment of patients withmalignant pleural mesothelioma - A pilot phase II clinical trial and pharmacokinetic profile
Authors: Nakano, T Chahinian, AP Shinjo, M Togawa, N Tonomura, A Miyake, M Ninomiya, K Yamamoto, T Higashino, K
Citation: T. Nakano et al., Cisplatin in combination with irinotecan in the treatment of patients withmalignant pleural mesothelioma - A pilot phase II clinical trial and pharmacokinetic profile, CANCER, 85(11), 1999, pp. 2375-2384
A high-level synthesis system for digital signal processing based on data-flow graph enumeration
Authors: Togawa, N Hisaki, T Yanagisawa, M Ohtsuki, T
Citation: N. Togawa et al., A high-level synthesis system for digital signal processing based on data-flow graph enumeration, IEICE T FUN, E81A(12), 1998, pp. 2563-2575
Risultati: 1-10 |