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Results: 2
PRECISE FINAL-STATE DETERMINATION OF MISMATCHED CMOS LATCHES
Authors:
VANNOIJE WAM LIU WT NAVARRO J
Citation:
Wam. Vannoije et al., PRECISE FINAL-STATE DETERMINATION OF MISMATCHED CMOS LATCHES, IEEE journal of solid-state circuits, 30(5), 1995, pp. 607-611
A SAMPLING TECHNIQUE AND ITS CMOS IMPLEMENTATION WITH 1 GB S BANDWIDTH AND 25 PS RESOLUTION/
Authors:
GRAY CT LIU WT VANNOIJE WAM HUGHES TA CAVIN RK
Citation:
Ct. Gray et al., A SAMPLING TECHNIQUE AND ITS CMOS IMPLEMENTATION WITH 1 GB S BANDWIDTH AND 25 PS RESOLUTION/, IEEE journal of solid-state circuits, 29(3), 1994, pp. 340-349
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