Authors: XIE HY VRUDHULA SBK

Citation: Hy. Xie et Sbk. Vrudhula, A TECHNIQUE FOR ESTIMATING SIGNAL ACTIVITY IN LOGIC-CIRCUITS, Integrated computer-aided engineering, 5(2), 1998, pp. 141-151

Authors: LAI YT PEDRAM M VRUDHULA SBK

Citation: Yt. Lai et al., FORMAL VERIFICATION USING EDGE-VALUED BINARY DECISION DIAGRAMS, I.E.E.E. transactions on computers, 45(2), 1996, pp. 247-255

Authors: MACKEY RP RODRIGUEZ JJ CAROTHERS JD VRUDHULA SBK

Citation: Rp. Mackey et al., ASYNCHRONOUS VLSI ARCHITECTURE FOR ADAPTIVE ECHO CANCELLATION, Electronics Letters, 32(8), 1996, pp. 710-711

Authors: MAJUMDAR A VRUDHULA SBK

Citation: A. Majumdar et Sbk. Vrudhula, FAULT COVERAGE AND TEST LENGTH ESTIMATION FOR RANDOM PATTERN TESTING, I.E.E.E. transactions on computers, 44(2), 1995, pp. 234-247

Authors: LAI YT PEDRAM M VRUDHULA SBK

Citation: Yt. Lai et al., EVBDD-BASED ALGORITHMS FOR INTEGER LINEAR-PROGRAMMING, SPECTRAL TRANSFORMATION, AND FUNCTION DECOMPOSITION, IEEE transactions on computer-aided design of integrated circuits and systems, 13(8), 1994, pp. 959-975

Authors: HO KC VRUDHULA SBK

Citation: Kc. Ho et Sbk. Vrudhula, INTERVAL GRAPH ALGORITHMS FOR 2-DIMENSIONAL MULTIPLE FOLDING OF ARRAY-BASED VLSI LAYOUTS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(10), 1994, pp. 1201-1222