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Results: 1-12 |
Results: 12
The influence of polysilicon gate morphology on dopant activation and deactivation kinetics in deep-submicron CMOS transistors
Authors: Cubaynes, FN Stolk, PA Verhoeven, J Roozeboom, F Woerlee, PH
Citation: Fn. Cubaynes et al., The influence of polysilicon gate morphology on dopant activation and deactivation kinetics in deep-submicron CMOS transistors, MAT SC S PR, 4(4), 2001, pp. 351-356
Growth and properties of LPCVD W-Si-N barrier layers
Authors: Bystrova, S Holleman, J Woerlee, PH
Citation: S. Bystrova et al., Growth and properties of LPCVD W-Si-N barrier layers, MICROEL ENG, 55(1-4), 2001, pp. 189-195
Copper chemical mechanical polishing using a slurry-free technique
Authors: Nguyen, VH Hof, AJ van Kranenburg, H Woerlee, PH Weimar, F
Citation: Vh. Nguyen et al., Copper chemical mechanical polishing using a slurry-free technique, MICROEL ENG, 55(1-4), 2001, pp. 305-312
RF-CMOS performance trends
Authors: Woerlee, PH Knitel, MJ van Langevelde, R Klaassen, DBM Tiemeijer, LF Scholten, AJ Duijnhoven, ATAZV
Citation: Ph. Woerlee et al., RF-CMOS performance trends, IEEE DEVICE, 48(8), 2001, pp. 1776-1782
Effect of heating ramp rates on transient enhanced diffusion in ion-implanted silicon
Authors: Mannino, G Stolk, PA Cowern, NEB de Boer, WB Dirks, AG Roozeboom, F van Berkum, JGM Woerlee, PH Toan, NN
Citation: G. Mannino et al., Effect of heating ramp rates on transient enhanced diffusion in ion-implanted silicon, APPL PHYS L, 78(7), 2001, pp. 889-891
Modeling of light-emission spectra measured on silicon nanometer-scale diode antifuses
Authors: Akil, N Houtsma, VE LeMinh, P Holleman, J Zieren, V de Mooij, D Woerlee, PH van den Berg, A Wallinga, H
Citation: N. Akil et al., Modeling of light-emission spectra measured on silicon nanometer-scale diode antifuses, J APPL PHYS, 88(4), 2000, pp. 1916-1922
High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates
Authors: Ponomarev, YV Stolk, PA Salm, C Schmitz, J Woerlee, PH
Citation: Yv. Ponomarev et al., High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates, IEEE DEVICE, 47(4), 2000, pp. 848-855
Stress-induced leakage current in p(+) poly MOS capacitors with poly-Si and Poly-Si0.7Ge0.3 gate material
Authors: Houtsma, VE Holleman, J Salm, C Widdershoven, FP Woerlee, PH
Citation: Ve. Houtsma et al., Stress-induced leakage current in p(+) poly MOS capacitors with poly-Si and Poly-Si0.7Ge0.3 gate material, IEEE ELEC D, 20(7), 1999, pp. 314-316
Dopant profile engineering of advanced Si MOSFET's using ion implantation
Authors: Stolk, PA Ponomarev, YV Schmitz, J van Brandenburg, ACMC Roes, R Montree, AH Woerlee, PH
Citation: Pa. Stolk et al., Dopant profile engineering of advanced Si MOSFET's using ion implantation, NUCL INST B, 148(1-4), 1999, pp. 242-246
SILC in MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material
Authors: Houtsma, VE Holleman, J Salm, C Woerlee, PH
Citation: Ve. Houtsma et al., SILC in MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material, MICROEL ENG, 48(1-4), 1999, pp. 415-418
1/f noise in polycrystalline SiGe analyzed in terms of mobility fluctuations
Authors: Chen, XY Salm, C Hooge, FN Woerlee, PH
Citation: Xy. Chen et al., 1/f noise in polycrystalline SiGe analyzed in terms of mobility fluctuations, SOL ST ELEC, 43(9), 1999, pp. 1715-1724
Deposited inter-polysilicon dielectrics for nonvolatile memories
Authors: Klootwijk, JH van Kranenburg, H Woerlee, PH Wallinga, H
Citation: Jh. Klootwijk et al., Deposited inter-polysilicon dielectrics for nonvolatile memories, IEEE DEVICE, 46(7), 1999, pp. 1435-1445
Risultati: 1-12 |