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Results: 1-3 |
Results: 3

Authors: Hoenigschmid, H Frey, A DeBrosse, JK Kirihata, T Mueller, G Storaska, DW Daniel, G Frankowsky, G Guay, KP Hanson, DR Hsu, LLC Ji, B Netis, DG Panaroni, S Radens, C Reith, AM Terletzki, H Weinfurtner, O Alsmeier, J Weber, W Wordeman, MR
Citation: H. Hoenigschmid et al., A 7F(2) cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's, IEEE J SOLI, 35(5), 2000, pp. 713-718

Authors: Takahashi, O Dhong, SH Ohkubo, M Onishi, S Dennard, RH Hannon, R Crowder, S Iyer, SS Wordeman, MR Davari, B Weinberger, WB Aoki, N
Citation: O. Takahashi et al., 1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro, IEEE J SOLI, 35(11), 2000, pp. 1673-1679

Authors: Kirihata, T Mueller, G Ji, B Frankowsky, G Ross, JM Terletzki, H Netis, DG Weinfurtner, O Hanson, DR Daniel, G Hsu, LLC Storaska, DW Reith, AM Hug, MA Guay, KP Selz, M Poechmueller, P Hoenigschmid, H Wordeman, MR
Citation: T. Kirihata et al., A 390-mm(2), 16-bank, l-Gb DDR SDRAM with hybrid bitline architecture, IEEE J SOLI, 34(11), 1999, pp. 1580-1588
Risultati: 1-3 |