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Results:
1-6
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Results: 6
A mixed mode BIST scheme based on reseeding of folding counters
Authors:
Hellebrand, S Liang, HG Wunderlich, HJ
Citation:
S. Hellebrand et al., A mixed mode BIST scheme based on reseeding of folding counters, J ELEC TEST, 17(3-4), 2001, pp. 341-349
Application of deterministic logic BIST on industrial circuits
Authors:
Kiefer, G Vranken, H Marinissen, EJ Wunderlich, HJ
Citation:
G. Kiefer et al., Application of deterministic logic BIST on industrial circuits, J ELEC TEST, 17(3-4), 2001, pp. 351-362
Deterministic BIST with partial scan
Authors:
Kiefer, G Wunderlich, HJ
Citation:
G. Kiefer et Hj. Wunderlich, Deterministic BIST with partial scan, J ELEC TEST, 16(3), 2000, pp. 169-177
Minimized power consumption for scan-based BIST
Authors:
Gerstendorfer, S Wunderlich, HJ
Citation:
S. Gerstendorfer et Hj. Wunderlich, Minimized power consumption for scan-based BIST, J ELEC TEST, 16(3), 2000, pp. 203-212
Deterministic BIST with multiple scan chains
Authors:
Kiefer, G Wunderlich, HJ
Citation:
G. Kiefer et Hj. Wunderlich, Deterministic BIST with multiple scan chains, J ELEC TEST, 14(1-2), 1999, pp. 85-93
BIST for systems-on-a-chip
Authors:
Wunderlich, HJ
Citation:
Hj. Wunderlich, BIST for systems-on-a-chip, INTEGRATION, 26(1-2), 1998, pp. 55-78
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