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Results: 1-9 |
Results: 9
DATA REDUCTION IN MEASUREMENT OF SIZE DISTRIBUTION USING SEDIMENTATION BALANCE METHOD
Authors: FUKUI K MIZUTA H SHIBA M YUN CM YOSHIDA H
Citation: K. Fukui et al., DATA REDUCTION IN MEASUREMENT OF SIZE DISTRIBUTION USING SEDIMENTATION BALANCE METHOD, Kagaku kogaku ronbunshu, 24(6), 1998, pp. 928-933
EFFECT OF PACKING STRUCTURE ON SEPARATION PERFORMANCE OF PACKED-BED
Authors: SAKAGUCHI H ADACHI K ISHIKI Y FUKUI K MA JF YUN CM SHINODA E YOSHIDA H
Citation: H. Sakaguchi et al., EFFECT OF PACKING STRUCTURE ON SEPARATION PERFORMANCE OF PACKED-BED, Kagaku kogaku ronbunshu, 24(1), 1998, pp. 37-41
3-DIMENSIONAL NUMERICAL-SIMULATION IN CYC LONE CLASSIFIER USING DIRECT METHOD
Authors: YAMAMOTO T OKANISHI K WATANABE S MA J SHINODA E YUN CM FUKUI K YOSHIDA H
Citation: T. Yamamoto et al., 3-DIMENSIONAL NUMERICAL-SIMULATION IN CYC LONE CLASSIFIER USING DIRECT METHOD, Kagaku kogaku ronbunshu, 23(6), 1997, pp. 885-891
COMPARISON OF LATERAL IGBT AND LATERAL EMITTER SWITCHED THYRISTOR WITH A PARTIAL BURIED OXIDE LAYER
Authors: YUN CM KIM JH HAN MK CHOI YI
Citation: Cm. Yun et al., COMPARISON OF LATERAL IGBT AND LATERAL EMITTER SWITCHED THYRISTOR WITH A PARTIAL BURIED OXIDE LAYER, Physica scripta. T, T69, 1997, pp. 341-344
DEVELOPMENT OF UNIPOLAR ION GENERATOR - SEPARATION OF IONS IN AXIAL DIRECTION OF FLOW
Authors: YUN CM OTANI Y EMI H
Citation: Cm. Yun et al., DEVELOPMENT OF UNIPOLAR ION GENERATOR - SEPARATION OF IONS IN AXIAL DIRECTION OF FLOW, Aerosol science and technology, 26(5), 1997, pp. 389-397
NUMERICAL-ANALYSIS OF A NEW VERTICAL IGBT STRUCTURE WITH REDUCED JFETEFFECT
Authors: YUN CM KIM DY HAN MK CHOI YI
Citation: Cm. Yun et al., NUMERICAL-ANALYSIS OF A NEW VERTICAL IGBT STRUCTURE WITH REDUCED JFETEFFECT, Solid-state electronics, 39(8), 1996, pp. 1179-1183
A NEW POWER MOSFET WITH SELF CURRENT LIMITING CAPABILITY
Authors: YUN CM HAN MK CHOI YI
Citation: Cm. Yun et al., A NEW POWER MOSFET WITH SELF CURRENT LIMITING CAPABILITY, International journal of electronics, 80(2), 1996, pp. 131-142
A TRENCH-GATE SILICON-ON-INSULATOR LATERAL INSULATED GATE BIPOLAR-TRANSISTOR WITH THE P(+) CATHODE WELL
Authors: LEE BH YUN CM BYEON DS HAN MK CHOI YI
Citation: Bh. Lee et al., A TRENCH-GATE SILICON-ON-INSULATOR LATERAL INSULATED GATE BIPOLAR-TRANSISTOR WITH THE P(+) CATHODE WELL, JPN J A P 1, 34(2B), 1995, pp. 854-859
LATCH-UP SUPPRESSED INSULATED GATE BIPOLAR-TRANSISTOR BY THE DEEP P(-IMPLANTATION UNDER THE N(+) SOURCE() ION)
Authors: LEE BH YUN CM KIM HS HAN MK CHOI YI
Citation: Bh. Lee et al., LATCH-UP SUPPRESSED INSULATED GATE BIPOLAR-TRANSISTOR BY THE DEEP P(-IMPLANTATION UNDER THE N(+) SOURCE() ION), JPN J A P 1, 33(1B), 1994, pp. 563-566
Risultati: 1-9 |