AAAAAA

   
Results: 1-11 |
Results: 11
A large-scale packet switch system and 60-Gbps pulse arbitration circuit operation using single flux quantum technology
Authors: Yorozu, S Kameda, Y Tahara, S
Citation: S. Yorozu et al., A large-scale packet switch system and 60-Gbps pulse arbitration circuit operation using single flux quantum technology, JPN J A P 1, 40(4B), 2001, pp. 2593-2596
SFQ standard cell-based circuit design of an internal link speeded-up Batcher-Banyan packet switch
Authors: Kameda, Y Yorozu, S Tahara, S
Citation: Y. Kameda et al., SFQ standard cell-based circuit design of an internal link speeded-up Batcher-Banyan packet switch, IEEE APPL S, 11(1), 2001, pp. 322-325
Superconducting digital electronics
Authors: Tahara, S Yorozu, S Kameda, Y Hashimoto, Y Numata, H Satoh, T Hattori, W Hidaka, M
Citation: S. Tahara et al., Superconducting digital electronics, IEEE APPL S, 11(1), 2001, pp. 463-468
60 Gbps throughput demonstration of an asynchronous SFQ-pulse arbitration circuit
Authors: Yorozu, S Kameda, Y Tahara, S
Citation: S. Yorozu et al., 60 Gbps throughput demonstration of an asynchronous SFQ-pulse arbitration circuit, IEEE APPL S, 11(1), 2001, pp. 621-624
An SFQ-based high-performance packet switch for next-generation high-end routers
Authors: Yorozu, S Kameda, Y Tahara, S
Citation: S. Yorozu et al., An SFQ-based high-performance packet switch for next-generation high-end routers, PHYSICA C, 357, 2001, pp. 1540-1543
A hybrid switch system architecture for large-scale digital communication network using SFQ technology
Authors: Yorozu, S Kameda, Y Tahara, S
Citation: S. Yorozu et al., A hybrid switch system architecture for large-scale digital communication network using SFQ technology, IEICE TR EL, E84C(1), 2001, pp. 15-19
Superconducting technology for digital applications using niobium Josephson junctions
Authors: Tahara, S Numata, H Yorozu, S Hashimoto, Y Nagasawa, S
Citation: S. Tahara et al., Superconducting technology for digital applications using niobium Josephson junctions, IEICE TR EL, E83C(1), 2000, pp. 60-68
System demonstration of a superconducting communication system
Authors: Yorozu, S Hashimoto, Y Numata, H Nagasawa, S Tahara, S
Citation: S. Yorozu et al., System demonstration of a superconducting communication system, IEEE APPL S, 9(2), 1999, pp. 2975-2980
Clock-driven on-chip testing for superconductor logic circuits
Authors: Hashimoto, Y Yorozu, S Numata, H Tahara, S
Citation: Y. Hashimoto et al., Clock-driven on-chip testing for superconductor logic circuits, IEEE APPL S, 9(2), 1999, pp. 3169-3172
Design and implementation of an RSFQ switching node for petaflops networks
Authors: Yorozu, S Zinoviev, DY Sazaklis, G
Citation: S. Yorozu et al., Design and implementation of an RSFQ switching node for petaflops networks, IEEE APPL S, 9(2), 1999, pp. 3557-3560
Full operation of a three-node pipeline-ring switching chip for a superconducting network system
Authors: Yorozu, S Hashimoto, Y Numata, H Koike, M Tanaka, M Tahara, S
Citation: S. Yorozu et al., Full operation of a three-node pipeline-ring switching chip for a superconducting network system, IEEE APPL S, 9(2), 1999, pp. 3590-3593
Risultati: 1-11 |