Authors: van Meer, H De Meyer, K

Citation: H. Van Meer et K. De Meyer, Threshold voltage model for deep-submicron fully depleted SOICMOS transistors including the effect of source/drain fringing fields into the buried oxide, SOL ST ELEC, 45(4), 2001, pp. 593-598

Authors: van Meer, H De Meyer, K

Citation: H. Van Meer et K. De Meyer, A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with halos or pockets, IEEE DEVICE, 48(10), 2001, pp. 2292-2302

Authors: van Meer, H Henson, K Lyu, JH Rosmeulen, M Kubicek, S Collaert, N De Meyer, K

Citation: H. Van Meer et al., Limitations of shift-and-ratio based L-eff extraction techniques for MOS transistors with halo or pocket implants, IEEE ELEC D, 21(3), 2000, pp. 133-136

Authors: Simoen, E van Meer, H Valenza, M van der Zanden, K De Raedt, W

Citation: E. Simoen et al., Low-frequency gate current noise of InP based HEMTs, SOL ST ELEC, 43(9), 1999, pp. 1797-1800