We have assembled an integrated view of the entire via manufacturing p
rocess, This integrated study includes five key plasma processes that
culminate in the production of vias on CMOS wafers, There are essentia
lly no linear cross-correlations between the processing steps and ther
e are no linear correlations between the individual process steps and
the yield for vias, as measured by the resistance between metal-one (M
1) and metal-two (M2). Using a neural network, we demonstrate that the
key processing steps to determine the M1M2 resistance are the thick o
xide deposition and the anisotropic via etch, Of lesser significance a
re the etchback planarization, an isotropic etch and plasma enhanced t
etra-ethoxy siliane (PETEOS) deposition, Keeping in mind that there ar
e five processing steps, the numerical value of M1M2 resistance can be
predicted ahead of time, before completion of all five processes, Thi
s prediction can be done to an accuracy of about 1 Omega. By using ada
ptive neural networks, the intelligent agents can modify their predict
ive behavior with respect to process changes effected by the engineeri
ng staff, Our pre-production demonstration suggests that these program
s could be used in feedback and feedforward control for production yie
ld.