AUTOMATED EVALUATION OF CRITICAL FEATURES IN VLSI LAYOUTS BASED ON PHOTOLITHOGRAPHIC SIMULATIONS

In this paper, we address the problem of identifying and evaluating '' critical features'' in an integrated circuit (IC) layout, The ''critic al features'' (e.g., nested elbows and open ends) are areas in the lay out that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the ship area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used, Under these conditions, the only m eans to design compact circuits with good yield capabilities is to bri ng the design and process phases of IC manufacturing closer, This can be accomplished by integrating photolithography simulators with layout editors, However, evaluation of a large layout using a photolithograp hy simulator is time consuming and often unnecessary, A much faster an d efficient method would be to have a means of automatically identifyi ng ''critical features'' in a layout and then evaluate the ''critical features'' using a photolithography simulator. Our technique has poten tial for use either to evaluate the limits of any new and nonconventio nal process technique in an early process definition phase or in a mas k house, as a postprocessor to improve the printing capability of a gi ven mask. This paper presents a CAD tool (An Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulat or, Depict 3.0, that automatically identifies and evaluates ''critical features.''