YIELD ENHANCEMENT EFFECTS OF BOOSTED DUAL WORD-LINE (BDWL) SCHEME FORHIGH-DENSITY DRAMS

This paper describes the yield enhancement effects of a boosted dual w ord-line (BDWL) scheme for the 1st Al wiring in high density DRAM's, w ith a defect density model and a yield model used for comparison with that of the commonlmy used word-shunt (WS) scheme, Additionally, the y ield of 1st Al wiring with a step height between memory cell array and peripheral circuit regions is also estimated, The yield estimation de monstrated that the yield enhancement effect of the wide Ist Al wiring for the BDWL scheme was comparable with or surpassed that of the redu ndancy for the WS scheme yield, when the Ist Al wiring pitch over the memory cell array of a BDWL scheme was over 4 times wider than that of the WS scheme, The yield estimation with step height indicated that t he 1st Al wiring yield of the BDWL scheme with the step height exceede d that of the WS scheme with the step height of zero, even if using so me global planarization technology.