A QUEUING NETWORK MODEL FOR SEMICONDUCTOR MANUFACTURING

Citation
Dp. Connors et al., A QUEUING NETWORK MODEL FOR SEMICONDUCTOR MANUFACTURING, IEEE transactions on semiconductor manufacturing, 9(3), 1996, pp. 412-427
Citations number
23
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing","Physics, Applied
ISSN journal
08946507
Volume
9
Issue
3
Year of publication
1996
Pages
412 - 427
Database
ISI
SICI code
0894-6507(1996)9:3<412:AQNMFS>2.0.ZU;2-E
Abstract
We develop an open queueing network model for rapid performance analys is of semiconductor manufacturing facilities. While the use of queuein g models for performance evaluation of manufacturing systems is not ne w, our approach differs from others in the detailed ways in which we m odel the different tool groups found in semiconductor wafer fabricatio n, as well as the way in which we characterize the effect of rework an d scrap on wafer lot sizes. As an application of the model, we describ e a method for performing tool planning for semiconductor lines, The m ethod is based on a marginal allocation procedure which uses performan ce estimates from the queueing network model to determine the number o f tools needed to achieve a target cycle time, with the objective bein g to minimize overall equipment cost.