SRAM BITMAP SHAPE-RECOGNITION AND SORTING USING NEURAL NETWORKS

This paper details the use of neural network technologies in the chara cterization of bit fail patterns occurring on SRAM chips as an alterna tive to the more traditional rule-based or knowledge-based approach to fail pattern occurrence and classification analysis, The results of b it fail pattern count analyses are used both for fault analysis post-p rocessing and manufacturing yield improvement methodologies, The move toward neural network implementation comes in response to prohibitivel y long processing times required for implementation of rule-based algo rithms on more complex devices and the added flexibility of a neural n etwork to learn new fail types in a more adaptive mode, An unsupervise d approach to fail pattern identification was implemented on a 128 K S RAM chip using a two-layer Kohonen Self Organizing Map for identificat ion and concurrence of bit fail pattern categories within SRAM chips, A second network utilized a multilayer perceptron (MLP) architecture w ith backpropagation of error for prediction of the number of occurrenc es per bitmap of each of the 34 previously identified shape types, The MLP used the output of a SOM as its input vector to assist in the fea ture extraction by shape type, Both trained networks out-performed exi sting rule-based algorithms both in ability to identify bit fail patte rn types, frequency counts, and speed of processing.