A METHOD FOR MODELING THE MANUFACTURABILITY OF IC DESIGNS

A methodology for modeling the manufacturability of MOS circuits has b een developed. The fabrication line is described using a small set of measurable process parameters, whose variation explains the range of c ircuit performance seen during production. These same parameters form the basis of a statistical MOSFET model which combines physical measur ements, global optimization, and regression modeling of key fitting pa rameters to accurately predict transistor characteristics over a wide range of process variation. The fabrication line description in conjun ction with the MOSFET model was used to develop a manufacturing applic ation, specifically, a performance prediction model which uses the pro cess parameters as measured on the manufacturing floor to predict the performance of fabricated integrated circuits before packaging and fin al test. The MOSFET model and the performance prediction model are int egrated, and data taken from the manufacturing line can be used to ver ify the models, to identify process shifts, and suggest design improve ments for further manufacturability enhancements. The method was succe ssfully applied to an industrial 1.5-mum CMOS process, and models were developed and tested for a 1-Mbit EPROM.