Y. Pan et al., A NEW METHOD FOR DETECTING THE POLYSILICON GATE REENTRANT OF THE SUBMICRON LDD MOSFETS, IEEE transactions on semiconductor manufacturing, 7(4), 1994, pp. 460-462
With the continued shrinkage of the CMOS devices to the deep submicron
regime, the control of the gate-to-drain overlap is becoming a string
ent problem. We report that the gate-to-drain (source) current of an L
DD p-MOSFET under a high positive gate-to-drain (source) bias is stron
gly correlated to the oxide thickness in the polysilicon gate edge and
, consequently, to the gate-to-drain overlap capacitance. A simple phy
sical model is then constructed to explain the observed correlation. M
onitoring the poly gate reentrant by measuring the gate-to-drain curre
nt is simple and can be easily implemented in the parametric electrica
l tests in a process line.