AN ELECTRICAL TEST STRUCTURE FOR THE MEASUREMENT OF PLANARIZATION

This paper presents the simulation and experimental measurements of an electrical test structure that can be used to assess the degree of pl anarization of interlayer dielectrics, It consists of two sets of meta l combs separated by a dielectric. For each structure the combs on the two layers overlap each other, with adjacent structures having the ov erlap in one direction progressionally offset by 0.2 mu m. The capacit ance of these structures is then measured, from which the degree of pl anarization can be assessed, This structure has potential applications for characterising chemical mechanical polishing (CMP) processes for multilevel very large scale integration (VLSI) applications.