IN-LINE YIELD PREDICTION METHODOLOGIES USING PATTERNED WAFER INSPECTION INFORMATION

Due to the advances in in-line inspection technology it is now possibl e to obtain an early in-line prediction of yield, This paper introduce s and compares two new in-line yield prediction methodologies: 1) mult ilayer critical area method and 2) defect-type-size kill-ratio method, These methods are more accurate than the past and other current appro aches used in the semiconductor industry, The first method uses the de sign layout information along;vith the in-line defect data, whereas th e second method uses the defect and field data to empirically derive t he kill-ratios. We demonstrate our methodologies using data collected in a real wafer fabrication facility at the polysilicon gate (poly), a nd the first and second interconnect (Metal 1 and Metal 2) post etch i nspection layers. We compare our in-line predictions with the actual y ield.