MODEL-FREE ESTIMATION OF DEFECT CLUSTERING IN INTEGRATED-CIRCUIT FABRICATION

This paper describes a model-free method for estimating some yield met rics that are used to track integrated circuit fabrication processes. Our method uses binary probe test data at the wafer level to estimate the size, shape and location of large-area defects or clusters of defe ctive chips, Unlike previous methods in the yield modeling Literature, our approach makes extensive use of the location of failing chips to directly identify clusters, An important byproduct of this analysis is a decomposition of wafer yield that attributes defective chips to eit her large- or small-area defects, Simulation studies show that our pro cedure is superior to the time-honored windowing technique for achievi ng a similar breakdown, In addition, by directly estimating defect clu sters, we can provide engineers with a greater understanding of the ma nufacturing process, It has been our experience that routine identific ation of the spatial signatures of clustered defects and associated ro ot-cause analysis is a cost-effective approach to yield and process im provement.