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Table of contents of journal: *IEEE journal of solid-state circuits

Results: 76-100/1395
SUBSTRATE NOISE COUPLING THROUGH PLANAR SPIRAL INDUCTOR
Authors: PUN ALL YEUNG T LAU J CLEMENT FJR SU DK
Citation: All. Pun et al., SUBSTRATE NOISE COUPLING THROUGH PLANAR SPIRAL INDUCTOR, IEEE journal of solid-state circuits, 33(6), 1998, pp. 877-884
ANALOG SYNTHESIS OF NONLINEAR FUNCTIONS BASED ON FUZZY-LOGIC
Authors: FRANCHI E MANARESI N ROVATTI R BELLINI A BACCARANI G
Citation: E. Franchi et al., ANALOG SYNTHESIS OF NONLINEAR FUNCTIONS BASED ON FUZZY-LOGIC, IEEE journal of solid-state circuits, 33(6), 1998, pp. 885-895
FLAG - A FLEXIBLE LAYOUT GENERATOR FOR ANALOG MOS-TRANSISTORS
Authors: MATHIAS H BERGERTOUSSAN J JACQUEMOD G GAFFIOT F LEHELLEY M
Citation: H. Mathias et al., FLAG - A FLEXIBLE LAYOUT GENERATOR FOR ANALOG MOS-TRANSISTORS, IEEE journal of solid-state circuits, 33(6), 1998, pp. 896-903
A 200-MHZ COMPLEX NUMBER MULTIPLIER USING REDUNDANT BINARY ARITHMETIC
Authors: SHIN KW SONG BS BACRANIA K
Citation: Kw. Shin et al., A 200-MHZ COMPLEX NUMBER MULTIPLIER USING REDUNDANT BINARY ARITHMETIC, IEEE journal of solid-state circuits, 33(6), 1998, pp. 904-909
DESIGN OF A SCALABLE PIPELINED RAM SYSTEM
Authors: JEONG GJ LEE MK
Citation: Gj. Jeong et Mk. Lee, DESIGN OF A SCALABLE PIPELINED RAM SYSTEM, IEEE journal of solid-state circuits, 33(6), 1998, pp. 910-914
LOW-VOLTAGE CLASS AB BUFFERS WITH QUIESCENT CURRENT CONTROL
Authors: YOU F EMBABI SHK SANCHEZSINENCIO E
Citation: F. You et al., LOW-VOLTAGE CLASS AB BUFFERS WITH QUIESCENT CURRENT CONTROL, IEEE journal of solid-state circuits, 33(6), 1998, pp. 915-920
A STUDY OF HOT-CARRIER-INDUCED MISMATCH DRIFT - A RELIABILITY ISSUE FOR VLSI CIRCUITS
Authors: HUH YJ SUNG YK KANG SM
Citation: Yj. Huh et al., A STUDY OF HOT-CARRIER-INDUCED MISMATCH DRIFT - A RELIABILITY ISSUE FOR VLSI CIRCUITS, IEEE journal of solid-state circuits, 33(6), 1998, pp. 921-927
A GENERAL-THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS (VOL 33, PG179, 1998)
Authors: HAJIMIRI A LEE TH
Citation: A. Hajimiri et Th. Lee, A GENERAL-THEORY OF PHASE NOISE IN ELECTRICAL OSCILLATORS (VOL 33, PG179, 1998), IEEE journal of solid-state circuits, 33(6), 1998, pp. 928-928
COMMENTS ON A 64-POINT FOURIER-TRANSFORM CHIP FOR VIDEO MOTION COMPENSATION USING PHASE CORRELATION
Authors: MCGEE KJ
Citation: Kj. Mcgee, COMMENTS ON A 64-POINT FOURIER-TRANSFORM CHIP FOR VIDEO MOTION COMPENSATION USING PHASE CORRELATION, IEEE journal of solid-state circuits, 33(6), 1998, pp. 928-932
SPECIAL ISSUE ON THE 1997 SYMPOSIUM ON VLSI CIRCUITS - FOREWORD
Authors: BIDERMANN W SAKURAI T
Citation: W. Bidermann et T. Sakurai, SPECIAL ISSUE ON THE 1997 SYMPOSIUM ON VLSI CIRCUITS - FOREWORD, IEEE journal of solid-state circuits, 33(5), 1998, pp. 674-675
HIGH-PERFORMANCE MICROPROCESSOR DESIGN
Authors: GRONOWSKI PE BOWHILL WJ PRESTON RP GOWAN MK ALLMON RL
Citation: Pe. Gronowski et al., HIGH-PERFORMANCE MICROPROCESSOR DESIGN, IEEE journal of solid-state circuits, 33(5), 1998, pp. 676-686
SELF-POWERED SIGNAL-PROCESSING USING VIBRATION-BASED POWER-GENERATION
Authors: AMIRTHARAJAH R CHANDRAKASAN AP
Citation: R. Amirtharajah et Ap. Chandrakasan, SELF-POWERED SIGNAL-PROCESSING USING VIBRATION-BASED POWER-GENERATION, IEEE journal of solid-state circuits, 33(5), 1998, pp. 687-695
A 32 X 32-B ADIABATIC REGISTER FILE WITH SUPPLY CLOCK GENERATOR
Authors: MOON Y JEONG DK
Citation: Y. Moon et Dk. Jeong, A 32 X 32-B ADIABATIC REGISTER FILE WITH SUPPLY CLOCK GENERATOR, IEEE journal of solid-state circuits, 33(5), 1998, pp. 696-701
A DATA-TRANSITION LOOK-AHEAD DFF CIRCUIT FOR STATISTICAL REDUCTION INPOWER-CONSUMPTION
Authors: NOGAWA M OHTOMO Y
Citation: M. Nogawa et Y. Ohtomo, A DATA-TRANSITION LOOK-AHEAD DFF CIRCUIT FOR STATISTICAL REDUCTION INPOWER-CONSUMPTION, IEEE journal of solid-state circuits, 33(5), 1998, pp. 702-706
ISSUE LOGIC FOR A 600-MHZ OUT-OF-ORDER EXECUTION MICROPROCESSOR
Authors: FARRELL JA FISCHER TC
Citation: Ja. Farrell et Tc. Fischer, ISSUE LOGIC FOR A 600-MHZ OUT-OF-ORDER EXECUTION MICROPROCESSOR, IEEE journal of solid-state circuits, 33(5), 1998, pp. 707-712
A 0.5-MU-M CMOS 4.0-GBIT S SERIAL LINK TRANSCEIVER WITH DATA RECOVERYUSING OVERSAMPLING/
Authors: YANG CKK FARJADRAD R HOROWITZ MA
Citation: Ckk. Yang et al., A 0.5-MU-M CMOS 4.0-GBIT S SERIAL LINK TRANSCEIVER WITH DATA RECOVERYUSING OVERSAMPLING/, IEEE journal of solid-state circuits, 33(5), 1998, pp. 713-722
A 950-MHZ IF 2ND-ORDER INTEGRATED LC BANDPASS DELTA-SIGMA MODULATOR
Authors: GAO WN SNELGROVE WM
Citation: Wn. Gao et Wm. Snelgrove, A 950-MHZ IF 2ND-ORDER INTEGRATED LC BANDPASS DELTA-SIGMA MODULATOR, IEEE journal of solid-state circuits, 33(5), 1998, pp. 723-732
A MULTIMODE DIGITAL-DETECTOR READOUT FOR SOLID-STATE MEDICAL IMAGING DETECTORS
Authors: BOLES CD BOSER BE HASEGAWA BH HEANUE JA
Citation: Cd. Boles et al., A MULTIMODE DIGITAL-DETECTOR READOUT FOR SOLID-STATE MEDICAL IMAGING DETECTORS, IEEE journal of solid-state circuits, 33(5), 1998, pp. 733-742
ON-CHIP SPIRAL INDUCTORS WITH PATTERNED-GROUND SHIELDS FOR SI-BASED RF ICS
Authors: YUE CP WONG SS
Citation: Cp. Yue et Ss. Wong, ON-CHIP SPIRAL INDUCTORS WITH PATTERNED-GROUND SHIELDS FOR SI-BASED RF ICS, IEEE journal of solid-state circuits, 33(5), 1998, pp. 743-752
A 75-MW 128-MHZ DS-CDMA BASEBAND DEMODULATOR FOR HIGH-SPEED WIRELESS APPLICATIONS
Authors: ONODERA KK GRAY PR
Citation: Kk. Onodera et Pr. Gray, A 75-MW 128-MHZ DS-CDMA BASEBAND DEMODULATOR FOR HIGH-SPEED WIRELESS APPLICATIONS, IEEE journal of solid-state circuits, 33(5), 1998, pp. 753-761
CMOS CHARGE-TRANSFER PREAMPLIFIER FOR OFFSET-FLUCTUATION CANCELLATIONIN LOW-POWER A D CONVERTERS/
Authors: KOTANI K SHIBATA T OHMI T
Citation: K. Kotani et al., CMOS CHARGE-TRANSFER PREAMPLIFIER FOR OFFSET-FLUCTUATION CANCELLATIONIN LOW-POWER A D CONVERTERS/, IEEE journal of solid-state circuits, 33(5), 1998, pp. 762-769
400-MHZ RANDOM COLUMN OPERATING SDRAM TECHNIQUES WITH SELF-SKEW COMPENSATION
Authors: HAMAMOTO T TSUKUDE M ARIMOTO K KONISHI Y MIYAMOTO T OZAKI H YAMADA M
Citation: T. Hamamoto et al., 400-MHZ RANDOM COLUMN OPERATING SDRAM TECHNIQUES WITH SELF-SKEW COMPENSATION, IEEE journal of solid-state circuits, 33(5), 1998, pp. 770-778
A 1 GBIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY WITH AN INDEPENDENTSUBARRAY-CONTROLLED SCHEME AND A HIERARCHICAL DECODING SCHEME
Authors: LEE K KIM CH YOON H KIM KY MOON BS LEE SB LEE JH KIM NJ CHO SI
Citation: K. Lee et al., A 1 GBIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY WITH AN INDEPENDENTSUBARRAY-CONTROLLED SCHEME AND A HIERARCHICAL DECODING SCHEME, IEEE journal of solid-state circuits, 33(5), 1998, pp. 779-786
HIGH-DENSITY CHAIN FERROELECTRIC RANDOM-ACCESS MEMORY (CHAIN FRAM)
Authors: TAKASHIMA D KUNISHIMA I
Citation: D. Takashima et I. Kunishima, HIGH-DENSITY CHAIN FERROELECTRIC RANDOM-ACCESS MEMORY (CHAIN FRAM), IEEE journal of solid-state circuits, 33(5), 1998, pp. 787-792
A CHARGE-TRANSFER AMPLIFIER AND AN ENCODED-BUS ARCHITECTURE FOR LOW-POWER SRAMS
Authors: KAWASHIMA S MORI T SASAGAWA R HAMAMINATO M WAKAYAMA S SUKEGAWA K FUKUSHI I
Citation: S. Kawashima et al., A CHARGE-TRANSFER AMPLIFIER AND AN ENCODED-BUS ARCHITECTURE FOR LOW-POWER SRAMS, IEEE journal of solid-state circuits, 33(5), 1998, pp. 793-799
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