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Results: 1-9 |
Results: 9
ON A UNIVERSAL PARAMETER OF INTRINSIC OXIDE BREAKDOWN BASED ON ANALYSIS OF TRAP-GENERATION CHARACTERISTICS
Authors: SAKAKIBARA K AJIKA N MIYOSHI H
Citation: K. Sakakibara et al., ON A UNIVERSAL PARAMETER OF INTRINSIC OXIDE BREAKDOWN BASED ON ANALYSIS OF TRAP-GENERATION CHARACTERISTICS, I.E.E.E. transactions on electron devices, 45(6), 1998, pp. 1336-1341
NEW BURIED-CHANNEL FLASH MEMORY CELL WITH SYMMETRICAL SOURCE DRAIN STRUCTURE/
Authors: ODA H UENO S AJIKA N INUISHI M MIYOSHI H
Citation: H. Oda et al., NEW BURIED-CHANNEL FLASH MEMORY CELL WITH SYMMETRICAL SOURCE DRAIN STRUCTURE/, Electronics & communications in Japan. Part 2, Electronics, 80(4), 1997, pp. 76-84
IDENTIFICATION OF STRESS-INDUCED LEAKAGE CURRENT COMPONENTS AND THE CORRESPONDING TRAP MODELS IN SIO2-FILMS
Authors: SAKAKIBARA K AJIKA N HATANAKA M MIYOSHI H YASUOKA A
Citation: K. Sakakibara et al., IDENTIFICATION OF STRESS-INDUCED LEAKAGE CURRENT COMPONENTS AND THE CORRESPONDING TRAP MODELS IN SIO2-FILMS, I.E.E.E. transactions on electron devices, 44(6), 1997, pp. 986-992
A QUANTITATIVE-ANALYSIS OF TIME-DECAY REPRODUCIBLE STRESS-INDUCED LEAKAGE CURRENT IN SIO2-FILMS
Authors: SAKAKIBARA K AJIKA N EIKYU K ISHIKAWA K MIYOSHI H
Citation: K. Sakakibara et al., A QUANTITATIVE-ANALYSIS OF TIME-DECAY REPRODUCIBLE STRESS-INDUCED LEAKAGE CURRENT IN SIO2-FILMS, I.E.E.E. transactions on electron devices, 44(6), 1997, pp. 1002-1008
IDENTIFICATION OF STRESS-INDUCED LEAKAGE CURRENT COMPONENTS AND THE CORRESPONDING TRAP MODELS IN SIO2-FILMS (VOL 44, PG 986, 1997)
Authors: SAKAKIBARA K AJIKA N HATANAKA M MIYOSHI H YASUOKA A
Citation: K. Sakakibara et al., IDENTIFICATION OF STRESS-INDUCED LEAKAGE CURRENT COMPONENTS AND THE CORRESPONDING TRAP MODELS IN SIO2-FILMS (VOL 44, PG 986, 1997), I.E.E.E. transactions on electron devices, 44(12), 1997, pp. 2267-2273
INFLUENCE OF HOLES ON NEUTRAL TRAP GENERATION
Authors: SAKAKIBARA K AJIKA N MIYOSHI H
Citation: K. Sakakibara et al., INFLUENCE OF HOLES ON NEUTRAL TRAP GENERATION, I.E.E.E. transactions on electron devices, 44(12), 1997, pp. 2274-2280
IMPROVED ARRAY ARCHITECTURES OF DINOR FOR 0.5 MU-M 32 M AND 64 MBIT FLASH MEMORIES
Authors: ONODA H KUNORI Y YUZURIHA K KOBAYASHI S SAKAKIBARA K OHI M FUKUMOTO A AJIKA N HATANAKA M MIYOSHI H
Citation: H. Onoda et al., IMPROVED ARRAY ARCHITECTURES OF DINOR FOR 0.5 MU-M 32 M AND 64 MBIT FLASH MEMORIES, IEICE transactions on electronics, E77C(8), 1994, pp. 1279-1286
MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3-V ONLY SECTOR ERASABLE DINOR FLASH MEMORY
Authors: KOBAYASHI S NAKAI H KUNORI Y NAKAYAMA T MIYAWAKI Y TERADA Y ONODA H AJIKA N HATANAKA M MIYOSHI H YOSHIHARA T
Citation: S. Kobayashi et al., MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3-V ONLY SECTOR ERASABLE DINOR FLASH MEMORY, IEICE transactions on electronics, E77C(5), 1994, pp. 784-790
MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3-V ONLY SECTOR ERASABLE DINOR FLASH MEMORY
Authors: KOBAYASHI S NAKAI H KUNORI Y NAKAYAMA T MIYAWAKI Y TERADA Y ONODA H AJIKA N HATANAKA M MIYOSHI H YOSHIHARA T
Citation: S. Kobayashi et al., MEMORY ARRAY ARCHITECTURE AND DECODING SCHEME FOR 3-V ONLY SECTOR ERASABLE DINOR FLASH MEMORY, IEEE journal of solid-state circuits, 29(4), 1994, pp. 454-460
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