Authors: Bellido-Diaz, MJ Juan-Chico, J Acosta, AJ Valencia, M Huertas, JL

Citation: Mj. Bellido-diaz et al., Logical modelling of delay degradation effect in static CMOS gates, IEE P-CIRC, 147(2), 2000, pp. 107-117

Authors: Yokota, K Kurahara, K Kataoka, D Tsujimoto, Y Acosta, AJ

Citation: K. Yokota et al., A study of swirling backflow and vortex structure at the inlet of an inducer, JSME I J B, 42(3), 1999, pp. 451-459

Authors: Garcia, TA Acosta, AJ Mora, JM Ramos, J Huertas, JL

Citation: Ta. Garcia et al., Self-timed boundary-scan cells for multi-chip module test, J ELEC TEST, 15(1-2), 1999, pp. 115-127

Authors: Juan-Chico, J Bellido, MJ Acosta, AJ Valencia, M

Citation: J. Juan-chico et al., Inertial effect handling method for CMOS digital IC simulation, ELECTR LETT, 35(23), 1999, pp. 2028-2030