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Results: 1-5 |
Results: 5

Authors: Muhammad, K Staszewski, RB Balsara, PT
Citation: K. Muhammad et al., Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels, IEEE VLSI, 9(1), 2001, pp. 42-51

Authors: Staszewski, RB Muhammad, K Balsara, PT
Citation: Rb. Staszewski et al., A constrained asymmetry LMS algorithm for PRML disk drive read channels, IEEE CIR-II, 48(8), 2001, pp. 793-798

Authors: Ko, UM Balsara, PT
Citation: Um. Ko et Pt. Balsara, High-performance energy-efficient D-flip-flop circuits, IEEE VLSI, 8(1), 2000, pp. 94-98

Authors: Koshy, KJ Balsara, PT
Citation: Kj. Koshy et Pt. Balsara, QMOS digital logic circuit design, INT J ELECT, 87(5), 2000, pp. 531-545

Authors: Mahant-Shetti, SS Balsara, PT Lemonds, C
Citation: Ss. Mahant-shetti et al., High performance low power away multiplier using temporal tiling, IEEE VLSI, 7(1), 1999, pp. 121-124
Risultati: 1-5 |