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Results: 1-7 |
Results: 7
Introducing redundant computations in RTL data paths for reducing BIST resources
Authors: Parulkar, I Gupta, SK Breuer, MA
Citation: I. Parulkar et al., Introducing redundant computations in RTL data paths for reducing BIST resources, ACM T DES A, 6(3), 2001, pp. 423-445
Fundamental CAD algorithms
Authors: Breuer, MA Sarrafzadeh, M Somenzi, F
Citation: Ma. Breuer et al., Fundamental CAD algorithms, IEEE COMP A, 19(12), 2000, pp. 1449-1475
Novel test pattern generators for pseudoexhaustive testing
Authors: Srinivasan, R Gupta, SK Breuer, MA
Citation: R. Srinivasan et al., Novel test pattern generators for pseudoexhaustive testing, IEEE COMPUT, 49(11), 2000, pp. 1228-1240
Estimation of BIST resources during high-level synthesis
Authors: Parulkar, I Gupta, SK Breuer, MA
Citation: I. Parulkar et al., Estimation of BIST resources during high-level synthesis, J ELEC TEST, 13(3), 1998, pp. 221-237
An IEEE 1149.1 compliant test control architecture
Authors: Mukherjee, D Breuer, MA
Citation: D. Mukherjee et Ma. Breuer, An IEEE 1149.1 compliant test control architecture, J ELEC TEST, 13(3), 1998, pp. 273-297
Allocation techniques for reducing BIST area overhead of data paths
Authors: Parulkar, I Gupta, SK Breuer, MA
Citation: I. Parulkar et al., Allocation techniques for reducing BIST area overhead of data paths, J ELEC TEST, 13(2), 1998, pp. 149-166
A unified approach for the synthesis of scalable and testable embedded architectures
Authors: Bhat, PB Aktouf, C Prasanna, VK Gupta, S Breuer, MA
Citation: Pb. Bhat et al., A unified approach for the synthesis of scalable and testable embedded architectures, FAULT-TOLERANT PARALLEL AND DISTRIBUTED SYSTEMS, 1998, pp. 213-230
Risultati: 1-7 |