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Results: 1-10 |
Results: 10
DIGRAPH VISUALIZATION USING A NEURAL ALGORITHM WITH A HEURISTIC ACTIVATION SCHEME
Authors: KUSNADI,"BEEBE C CAROTHERS JD
Citation: C. Kusnadi,"beebe et Jd. Carothers, DIGRAPH VISUALIZATION USING A NEURAL ALGORITHM WITH A HEURISTIC ACTIVATION SCHEME, IEEE transactions on systems, man and cybernetics. Part B. Cybernetics, 28(4), 1998, pp. 562-572
LOW-POWER VLSI DESIGN TECHNIQUES - THE CURRENT STATE
Authors: CAROTHERS JD RADJASSAMY R
Citation: Jd. Carothers et R. Radjassamy, LOW-POWER VLSI DESIGN TECHNIQUES - THE CURRENT STATE, Integrated computer-aided engineering, 5(2), 1998, pp. 153-175
HIERARCHICAL GRAPH VISUALIZATION USING NEURAL NETWORKS
Authors: KUSNADI,"CAROTHERS JD CHOW F
Citation: Jd. Kusnadi,"carothers et F. Chow, HIERARCHICAL GRAPH VISUALIZATION USING NEURAL NETWORKS, IEEE transactions on neural networks, 8(3), 1997, pp. 794-799
CONSIDERATION OF THERMAL CONSTRAINTS DURING MULTICHIP-MODULE PLACEMENT
Authors: TANG MC CAROTHERS JD
Citation: Mc. Tang et Jd. Carothers, CONSIDERATION OF THERMAL CONSTRAINTS DURING MULTICHIP-MODULE PLACEMENT, Electronics Letters, 33(12), 1997, pp. 1043-1045
FAST COUPLED NOISE ESTIMATION FOR CROSSTALK AVOIDANCE IN THE MCG MULTICHIP-MODULE AUTOROUTER
Authors: HAMEENANTTILA T CAROTHERS JD LI DH
Citation: T. Hameenanttila et al., FAST COUPLED NOISE ESTIMATION FOR CROSSTALK AVOIDANCE IN THE MCG MULTICHIP-MODULE AUTOROUTER, IEEE transactions on very large scale integration (VLSI) systems, 4(3), 1996, pp. 356-368
THE FLEXIBLE HYPERCUBE - A NEW FAULT-TOLERANT ARCHITECTURE FOR PARALLEL COMPUTING
Authors: HAMEENANTTILA T GUAN XL CAROTHERS JD CHEN JX
Citation: T. Hameenanttila et al., THE FLEXIBLE HYPERCUBE - A NEW FAULT-TOLERANT ARCHITECTURE FOR PARALLEL COMPUTING, Journal of parallel and distributed computing, 37(2), 1996, pp. 213-220
ASYNCHRONOUS VLSI ARCHITECTURE FOR ADAPTIVE ECHO CANCELLATION
Authors: MACKEY RP RODRIGUEZ JJ CAROTHERS JD VRUDHULA SBK
Citation: Rp. Mackey et al., ASYNCHRONOUS VLSI ARCHITECTURE FOR ADAPTIVE ECHO CANCELLATION, Electronics Letters, 32(8), 1996, pp. 710-711
CROSSTALK AVOIDANCE IN MCM ROUTING WITH TIMING CONSIDERATIONS
Authors: HAMEENANTTILA T CAROTHERS JD
Citation: T. Hameenanttila et Jd. Carothers, CROSSTALK AVOIDANCE IN MCM ROUTING WITH TIMING CONSIDERATIONS, Electronics Letters, 32(21), 1996, pp. 1950-1951
MCM ROUTING ALGORITHM-BASED ON A COMPATIBILITY GRAPH APPROACH
Authors: LI D CAROTHERS JD
Citation: D. Li et Jd. Carothers, MCM ROUTING ALGORITHM-BASED ON A COMPATIBILITY GRAPH APPROACH, Electronics Letters, 32(1), 1996, pp. 5-6
GRAPH-THEORETIC TECHNIQUES FOR COMPUTER INTRACONNECTION MINIMIZATION
Authors: CAROTHERS JD CRAGON HG
Citation: Jd. Carothers et Hg. Cragon, GRAPH-THEORETIC TECHNIQUES FOR COMPUTER INTRACONNECTION MINIMIZATION, IEEE transactions on systems, man, and cybernetics, 23(3), 1993, pp. 876-888
Risultati: 1-10 |