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Results: 3
A HYBRID RADIX-4 RADIX-8 LOW-POWER SIGNED MULTIPLIER ARCHITECTURE/
Authors: CHERKAUER BS FRIEDMAN EG
Citation: Bs. Cherkauer et Eg. Friedman, A HYBRID RADIX-4 RADIX-8 LOW-POWER SIGNED MULTIPLIER ARCHITECTURE/, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(8), 1997, pp. 656-659
A UNIFIED DESIGN METHODOLOGY FOR CMOS TAPERED BUFFERS
Authors: CHERKAUER BS FRIEDMAN EG
Citation: Bs. Cherkauer et Eg. Friedman, A UNIFIED DESIGN METHODOLOGY FOR CMOS TAPERED BUFFERS, IEEE transactions on very large scale integration (VLSI) systems, 3(1), 1995, pp. 99-111
DESIGN OF TAPERED BUFFERS WITH LOCAL INTERCONNECT CAPACITANCE
Authors: CHERKAUER BS FRIEDMAN EG
Citation: Bs. Cherkauer et Eg. Friedman, DESIGN OF TAPERED BUFFERS WITH LOCAL INTERCONNECT CAPACITANCE, IEEE journal of solid-state circuits, 30(2), 1995, pp. 151-155
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