Authors: RUDNICK EM CHICKERMANE V BANERJEE P PATEL JH

Citation: Em. Rudnick et al., SEQUENTIAL-CIRCUIT TESTABILITY ENHANCEMENT USING A NONSCAN APPROACH, IEEE transactions on very large scale integration (VLSI) systems, 3(2), 1995, pp. 333-338

Authors: RUDNICK EM CHICKERMANE V PATEL JH

Citation: Em. Rudnick et al., AN OBSERVABILITY ENHANCEMENT APPROACH FOR IMPROVED TESTABILITY AND AT-SPEED TEST, IEEE transactions on computer-aided design of integrated circuits and systems, 13(8), 1994, pp. 1051-1056

Authors: CHICKERMANE V LEE J PATEL JH

Citation: V. Chickermane et al., ADDRESSING DESIGN FOR TESTABILITY AT THE ARCHITECTURAL LEVEL, IEEE transactions on computer-aided design of integrated circuits and systems, 13(7), 1994, pp. 920-934