Authors: Celinski, P Lopez, JF Al-Sarawi, S Abbott, D

Citation: P. Celinski et al., Low power, high speed, charge recycling CMOS threshold logic gate, ELECTR LETT, 37(17), 2001, pp. 1067-1069

Authors: Celinski, P Abbott, D Al-Sarawi, SF Lopez, JF

Citation: P. Celinski et al., Novel extension of neu-MOS techniques to neu-GaAs, MICROELEC J, 31(7), 2000, pp. 577-582

Authors: Celinski, P Lopez, JF Al-Sarawi, S Abbott, D

Citation: P. Celinski et al., Complementary neu-GaAs structure, ELECTR LETT, 36(5), 2000, pp. 424-425