Authors: DIAZ CH KOPLEY TE MARCOUX PJ

Citation: Ch. Diaz et al., BUILDING-IN ESD EOS RELIABILITY FOR SUB-HALFMICRON CMOS PROCESSES/, I.E.E.E. transactions on electron devices, 43(6), 1996, pp. 991-999

Authors: DIAZ CH DUVVURY C KANG SM

Citation: Ch. Diaz et al., STUDIES OF EOS SUSCEPTIBILITY IN 0.6-MU-M NMOS ESD I O PROTECTION STRUCTURES/, Journal of electrostatics, 33(3), 1994, pp. 273-289

Authors: DIAZ CH KANG SM DUVVURY C

Citation: Ch. Diaz et al., CIRCUIT-LEVEL ELECTROTHERMAL SIMULATION OF ELECTRICAL OVERSTRESS FAILURES IN ADVANCED MOS I O PROTECTION DEVICES/, IEEE transactions on computer-aided design of integrated circuits and systems, 13(4), 1994, pp. 482-493

Authors: DIAZ CH KANG SM DUVVURY C

Citation: Ch. Diaz et al., SIMULATION OF ELECTRICAL OVERSTRESS THERMAL FAILURES IN INTEGRATED-CIRCUITS, I.E.E.E. transactions on electron devices, 41(3), 1994, pp. 359-366

Authors: DIAZ CH

Citation: Ch. Diaz, AUTOMATION OF ELECTRICAL OVERSTRESS CHARACTERIZATION FOR SEMICONDUCTOR-DEVICES, HEWLETT-PAC, 45(5), 1994, pp. 106-111