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Results: 1-5 |
Results: 5

Authors: Yamaguchi, K Fukaishi, M Sakamoto, T Akiyama, N Nakamura, K
Citation: K. Yamaguchi et al., A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture, IEEE J SOLI, 36(11), 2001, pp. 1666-1672

Authors: Fukaishi, M Nakamura, K Heiuchi, H Hirota, Y Nakazawa, Y Ikeno, H Hayama, H Yotsuyanagi, M
Citation: M. Fukaishi et al., A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays, IEEE J SOLI, 35(11), 2000, pp. 1611-1618

Authors: Kurisu, M Fukaishi, M Asazawa, H Nishikawa, M Nakamura, K Yotsuyanagi, M
Citation: M. Kurisu et al., Design innovations for multi-gigahertz-rate communication circuits with deep-submicron CMOS technology, IEICE TR EL, E82C(3), 1999, pp. 428-437

Authors: Fukaishi, M Nakamura, S Tajima, A Kinoshita, Y Suemura, Y Suzuki, H Itani, T Miyamoto, H Henmi, N Yamazaki, T Yotsuyanagi, M
Citation: M. Fukaishi et al., A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications, IEEE J SOLI, 34(9), 1999, pp. 1325-1330

Authors: Fukaishi, M Nakamura, K Sato, M Tsutsui, Y Kishi, S Yotsuyanagi, M
Citation: M. Fukaishi et al., A 4,25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture, IEEE J SOLI, 33(12), 1998, pp. 2139-2147
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